Memory system

ABSTRACT

A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.14/203,889, filed Mar. 11, 2014, and is based upon and claims thebenefit of priority from prior U.S. Provisional Application No.61/933,107, filed on Jan. 29, 2014, the entire contents of each of whichare incorporated herein by reference.

BACKGROUND

1. Field

The embodiment of the present invention relates to a memory system.

2. Description of the Related Art

As memory systems capable of storing mass data for use, variableresistance memories including cell arrays easily formable in threedimensions, such as a ReRAM (Resistance RAM) and an ion memory, havereceived attention.

In these memory systems, as one of methods for raising the density ofinformation storage, there is a method of fine pattering a cell array.The use of this method, however, requires higher technologies and causesa problem about cost rises. Another method includes multi-valuing acell. This method is an effective method because it causes almost nocost rise. In the case of this method, however, physical quantity levelsof a cell become unstable. Therefore, unprecedented different ideas arerequired for writing data to a cell, storing data by a cell and readingdata from a cell.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrative of an outline of a pair cell in amemory system according to the embodiment.

FIG. 2 is a diagram illustrative of assignments of information values tostates of the pair cell in the memory system according to theembodiment.

FIG. 3 is a diagram illustrative of assignments of information values tostates of the pair cell in the memory system according to theembodiment.

FIG. 4 is a diagram illustrative of assignments of information values tostates of the pair cell in the memory system according to theembodiment.

FIG. 5 is a diagram illustrative of assignments of information values tostates of the pair cell in the memory system according to theembodiment.

FIG. 6 is a diagram showing state variations of a cell in the memorysystem according to the embodiment.

FIG. 7 is a diagram showing a relation between relative inter-ionicdistances and activation energy in the cell in the memory systemaccording to the embodiment.

FIG. 8 is a diagram showing state variations of a cell in the memorysystem according to the embodiment.

FIG. 9 is a diagram showing a relation between relative inter-CNTdistances and activation energy in the cell in the memory systemaccording to the embodiment.

FIG. 10 is a graph showing relations among phonon energy within a NTstack, resistances of the NT stack, and potentials of the electric fieldwithin the NT stack in the memory system according to the embodiment.

FIG. 11 is a graph showing a relation between phonon energy and voltagesacross electrodes of a NT stack cell when the NT stack resistance ismade higher in the memory system according to the embodiment.

FIG. 12 is a graph showing a relation between phonon energy and cellcurrent in the NT stack when the NT stack resistance is made lower inthe memory system according to the embodiment.

FIG. 13 is a diagram showing a bias state of a cell array at the initialstep in a write sequence in the memory system according to theembodiment.

FIG. 14 is a diagram showing a bias state of a cell array at the all ‘0’write step in the write sequence in the memory system according to theembodiment.

FIG. 15 is a diagram showing a bias state of a cell array at the ‘L’write step in the write sequence in the memory system according to theembodiment.

FIG. 16 is a diagram showing potential variations on bit lines at thetime of the write sequence in the memory system according to theembodiment.

FIG. 17 is a diagram showing potential variations on word lines at thetime of the write sequence in the memory system according to theembodiment.

FIG. 18 is a schematic diagram of a configuration of reference bit linesin the memory system according to the embodiment.

FIG. 19 is a circuit diagram of a current source for reference bit linesin the memory system according to the embodiment.

FIG. 20 is a diagram illustrative of relations among comparison currentsat access operations in the memory system according to the embodiment.

FIG. 21 is a circuit diagram of a sense amp in the memory systemaccording to the embodiment.

FIG. 22 is a diagram of operating waveforms in the sense amp in thememory system according to the embodiment.

FIG. 23 is a circuit diagram showing a circuit on the reference inputside of the sense amp in the memory system according to the embodiment.

FIG. 24 is a diagram showing a configuration of a current sensing systemin the memory system according to the embodiment.

FIG. 25 is a diagram showing a layout of arrangement regions of verticallines in a cell array seen from the stacking direction in the memorysystem according to the embodiment.

FIG. 26 is a cross-sectional view of a transistor in the stackingdirection in the memory system according to the embodiment.

FIG. 27 is a diagram showing a layout of the cell array in the memorysystem according to the embodiment.

FIG. 28 is a diagram showing a layout of the cell array in the memorysystem according to the embodiment.

FIG. 29 is a diagram showing a layout of the cell array in the memorysystem according to the embodiment.

FIG. 30 is an equivalent circuit diagram of a VBL-structured cell arrayin the memory system according to the embodiment.

FIG. 31 is a functional block diagram of the memory system according tothe embodiment.

FIG. 32 is a flow chart of data processing in the memory systemaccording to the embodiment.

FIG. 33 is a flow chart of decoding in the memory system according tothe embodiment.

FIG. 34 is a block diagram of ECC processing in the memory systemaccording to the embodiment.

FIG. 35 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 36 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 37 is a diagram showing a block symbol of a circuit block in thememory system according to the embodiment.

FIG. 38 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 39 is a power correspondence table of elements in Zp in the memorysystem according to the embodiment.

FIG. 40 is a power correspondence table of elements in Zp in the memorysystem according to the embodiment.

FIG. 41 is a power correspondence table of elements in Zp in the memorysystem according to the embodiment.

FIG. 42 is a power correspondence table of elements in Zp in the memorysystem according to the embodiment.

FIG. 43 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 44 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 45 is a table showing divergences and syndromes of a searchingequation of Zp in the memory system according to the embodiment.

FIG. 46 is a correspondence table of elements in Zp, and inverseelements, squares and square roots thereof in the memory systemaccording to the embodiment.

FIG. 47 is a correspondence table of elements in Zp, and inverseelements, squares and square roots thereof in the memory systemaccording to the embodiment.

FIG. 48 is a correspondence table of elements in Zp, and inverseelements, squares and square roots thereof in the memory systemaccording to the embodiment.

FIG. 49 is a correspondence table of elements in Zp, and inverseelements, squares and square roots thereof in the memory systemaccording to the embodiment.

FIG. 50 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 51 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 52 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 53 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 54 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 55 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

FIG. 56 is a circuit diagram of a computation block in the memory systemaccording to the embodiment.

DETAILED DESCRIPTION

A memory system according to the embodiment comprises a cell array ofplural cells having three or more settable physical quantity levels andoperative to store a code composed of symbols expressed by elements in afinite field Zp (p is a prime), wherein a set of two cells is defined asa pair cell and a combination of physical quantity levels of the twocells contained in the pair cell is defined as a pair cell level,wherein the pair cell uses a pair cell level of plural pair cell levels,which maximizes or minimizes a physical quantity level of one cellcontained in the pair cell, to assign elements in the Zp to the paircell levels, thereby storing symbols of the code.

A memory system according to the embodiment is described below withreference to the drawings.

In multi-valuing a cell in a resistance variable memory, a problemarises because it is difficult to definitely write multi-values to acell. This is because physical quantity levels or resistance values ofthe cell and voltage/current conditions are determined by indefinitestatistical relations. In the case of a phase change memory of variableresistance memories, as a resistance value drift is large, a relativecode is used in data reading for multi-valuing. In the case of a cell,in which the presence/absence of a metal filament is assigned to astorage state, the filament is unstable. Accordingly, the filament orretention is stabilized, thereby stabilizing the resistance value formulti-valuing. In the case of a memory, in which nanotubes (hereinafteralso referred to as “NT”s) such as carbon nanotubes (hereinafter alsoreferred to as “CNT”s) are stacked in a cell (hereinafter also referredto as a “NT stack cell”), the set resistance is maintained stable by thework of inter-molecular forces. Even in the case of the NT stack memory,however, it is difficult to set a definite resistance value as describedabove. Therefore, making practical a resistance variable memoryincluding multi-valued cells requires studies of methods for ensuringthe reliability of data. Hereinafter, the stacked NTs may also bereferred to as a “NT stack”, and a memory including NT stack cells as an“NT stack memory”.

Then, in the embodiment, the NT stack memory is used as an example tohandle methods of multi-value writing, which are effective in theoverall memories including cells having indefinite resistance values andvoltage/current conditions. In compensation for the indefiniteness ofmulti-value writing, this example applies a method of writing a Leemetric code (hereinafter also referred to as an “LMC”), which is a fastECC (Error Correction Code), to a pair of cells (hereinafter referred toas a “pair cell”). This makes it possible to simplify verification andso forth at the time of resistance value setting and additionallysuppress the number λ of cells per information bit. If λ<1 can beachieved, it is possible to exert an effect corresponding to a shrinkequal to λ-times a memory chip size. This is not a shrink throughprocesses and accordingly it can be realized without any increase inprocess step costs.

The memory system according to the embodiment will now be describedbelow specifically.

First, an outline of a multi-valued pair cell is described.

FIG. 1 is a diagram illustrative of an outline of a pair cell in amemory system according to the embodiment.

For relatively stable setting of resistance values other than on/off toa cell in a resistance variable memory, the maximum number of levelsassigned to resistance values can be considered equal to around eight.If more levels are assigned, statistical variations in cells allow noerror in resistance values to be suppressed within one level. On theother hand, for increasing the quantity of information stored in a cell,it is desired to assign as many levels as possible to resistance values.Thus, it is required to assign eight levels or more at least. Then, inconsideration of the magnitude of the burden on setting multi-levels toa cell alone, the embodiment uses a pair cell to reduce the burden. Amethod of setting resistance values is described, which increases thenumber of resistance value levels settable in a pair cell as a unit toincrease the storage capacity of a memory while compensates for theincrease in cell share caused by the use of the pair cell to raise theinformation density. In this method, resistance value levels areassigned to information values so that failed resistance value settingcauses the minimum variation in information value, thereby utilizing theLMC efficiently. Specifically, a prime p is assigned to resistance valuelevels of a pair cell so that an error-caused variation in resistancevalue level of a pair cell falls within space between successive valuesof information.

The following description is given to assignments of information valuesto combinations of resistance value levels of a pair cell composed of4-level/cell cells (hereinafter also simply referred to as “states of apair cell” (pair cell levels)).

FIG. 2 is a diagram illustrative of assignments of information values tostates of a pair cell in the memory system according to the embodiment.A numeral in ( ) of FIG. 2 indicates the corresponding informationvalue. A bar graph in FIG. 2 schematically indicates cell currentflowing when a certain voltage is applied across a cell so that a largerhatched part indicates a larger flow of cell current. It is assumed thata high resistance state with the lowest cell current and a lowresistance state with the highest cell current can be set withoutcausing failed setting. On the precondition of this assumption, it isdesired that failed setting is not caused simultaneously in resistancevalues of two cells contained in the pair cell. Therefore, one cell inthe pair cell is always set to a high resistance state or a lowresistance state that allows cell current to become the lowest or thehighest.

In the case of 4-level/cell, states of a pair cell vary in 12 ways. Asan LMC utilizes a residue field of a prime p, information values areassigned to states of the pair cell where p=11. At this time, theassignment is executed in such a manner that one level error inresistance value of a cell caused by failed setting of a state of thepair cell becomes an error falling within a range of an informationvalue ±1. As shown in FIG. 2, an information value 5 is assigned to twostates of the pair cell so that a residue field of p=11 is assigned to12 states of the pair cell. In this case, the precondition preventsfailed setting from arising in two cells of the pair cellsimultaneously. Therefore, as shown with the arrows in FIG. 2, failedwriting is only allowed to occur between successive information values.

The efficiency of assignments of information values in FIG. 2 isdescribed here in relation to the LMC.

As an error in information value falls within a range of +1, errorcorrection is sufficient if it is ready for ε=1 where s is the maximumvalue of error correctable Lee metrics. In this example, however, errorcorrection is made ready for ε=2. This enables error correction whenerrors within a range of ±1 occur in two code symbols of a code having alength of p−1, and when an error within a range of ±2 occurs in one codesymbol of the code.

An LMC ECC of p=11 and ε=2 has a code length n=p−1=10 code symbols ofwhich symbols usable as data are equal to k=n−(ε+1)=7 in number. Inaddition, the number of information bits storable in two cells is equalto log₂ 11. Therefore, the number of cells/bit becomes λ=(2n)/(k log₂p)=0.826.

In a word, according to the example of assignments of information valuesin FIG. 2, even if the reliability of data is maintained by ECC whileusing the pair cell, the cell occupation area can be shrunk by 0.826times.

The following description is given to assignments of information valuesto states of a pair cell composed of 5-level/cell cells.

FIG. 3 is a diagram illustrative of assignments of information values tostates of a pair cell in the memory system according to the embodiment.The viewpoint, precondition and so forth in FIG. 3 are similar to thoseof FIG. 2.

In the case of 5-level/cell, states of a pair cell vary in 16 ways. Asan LMC utilizes a residue field of a prime p, information values areassigned to states of the pair cell where p=13. At this time, theassignment is executed in such a manner that one level error inresistance value of a cell caused by failed setting of a state of thepair cell becomes an error falling within a range of an informationvalue ±1. As shown in FIG. 3, information values 2, 6 and 11 are eachassigned to two states of the pair cell so that a residue field of p=13is assigned to 16 states of the pair cell. In this case, theprecondition prevents failed setting from arising in two cells of thepair cell simultaneously. Therefore, as shown with the arrows in FIG. 3,failed writing is only allowed to occur between successive informationvalues.

The efficiency of assignments of information values in FIG. 3 isdescribed here in relation to the LMC.

As an error in information value falls within a range of ±1, errorcorrection is sufficient if it is ready for F=1. In this example,however, error correction is made ready for ε=2. This enables errorcorrection when errors within a range of ±1 occur in two code symbols ofa code having a length of p−1, and when an error within a range of ±2occurs in one code symbol of the code.

An LMC ECC of p=13 and ε=2 has a code length n=p−1=12 code symbols ofwhich symbols usable as data are equal to k=n−(ε+1)=9 in number. Inaddition, the number of information bits storable in two cells is equalto log₂ 13. Therefore, the number of cells/bit becomes λ=(2n)/(k log₂p)=0.721.

In a word, according to the example of assignments of information valuesin FIG. 3, even if the reliability of data is maintained by ECC whileusing the pair cell, the cell occupation area can be shrunk by 0.721times.

The following description is given to assignments of information valuesto states of a pair cell composed of 6-level/cell cells.

FIG. 4 is a diagram illustrative of assignments of information values tostates of the pair cell in the memory system according to theembodiment. The viewpoint, precondition and so forth in FIG. 4 aresimilar to those of FIG. 2.

In the case of 6-level/cell, states of a pair cell vary in 20 ways. Asan LMC utilizes a residue field of a prime p, information values areassigned to states of the pair cell where p=17. At this time, theassignment is executed in such a manner that one level error inresistance value of a cell caused by failed setting of a state of thepair cell becomes an error falling within a range of an informationvalue ±1. As shown in FIG. 4, information values 3, 8 and 14 are eachassigned to two states of the pair cell so that a residue field of p=17is assigned to 20 states of the pair cell. In this case, theprecondition prevents failed setting from arising in two cells of thepair cell simultaneously. Therefore, as shown with the arrows in FIG. 4,failed writing is only allowed to occur between successive informationvalues.

The efficiency of assignments of information values in FIG. 4 isdescribed here in relation to the LMC.

As an error in information value falls within a range of ±1, errorcorrection is sufficient if it is ready for ε=1. In this example,however, error correction is made ready for ε=2. In this case, errorcorrection is possible when errors within a range of ±1 occur in twocode symbols of a code having a length of p−1, and when an error withina range of ±2 occurs in one code symbol of the code.

An LMC ECC of p=17 and ε=2 has a code length n=p−1=16 code symbols ofwhich symbols usable as data are equal to k=n−(ε+1)=13 in number. Inaddition, the number of information bits expressible by symbols composedof two cells is equal to log₂ 13. Therefore, the number of cells/bitbecomes λ=(2n)/(k log₂ p)=0.602.

In a word, according to the example of assignments of information valuesin FIG. 4, even if the reliability of data is maintained by ECC whileusing the pair cell, the cell occupation area can be shrunk by 0.602times.

The following description is given to other assignments of informationvalues to states of a pair cell composed of 6-level/cell cells.

FIG. 5 is a diagram illustrative of assignments of information values tostates of the pair cell in the memory system according to theembodiment. FIG. 5 shows an instance of a prime p=19. The viewpoint,precondition and so forth in FIG. 5 are similar to those of FIG. 2.

In the case of 6-level/cell, states of a pair cell vary in 20 ways. Asan LMC utilizes a residue field of a prime p, information values areassigned to states of the pair cell where p=19. At this time, theassignment is executed in such a manner that one level error inresistance value of a cell caused by failed setting of a state of thepair cell becomes an error falling within a range of an informationvalue ±1. As shown in FIG. 5, an information value 9 is assigned to twostates of the pair cell so that a residue field of p=19 is assigned to20 states of the pair cell. In this case, the precondition preventsfailed setting from arising in two cells of the pair cellsimultaneously. Therefore, as shown with the arrows in FIG. 5, failedwriting is only allowed to occur between successive information values.

The effect of assignments of information values in FIG. 5 is describedhere in relation to the LMC.

As an error in information value falls within a range of ±1, errorcorrection is sufficient if it is ready for ε=1. In this example,however, error correction is made ready for ε=2. This enables errorcorrection when errors within a range of ±1 occur in two code symbols ofa code having a length of p−1, and when an error within a range of ±2occurs in one code symbol of the code.

An LMC ECC of p=19 and ε=2 has a code length n=p−1=18 code symbols ofwhich symbols usable as data are equal to k=n−(ε+1)=15 in number. Inaddition, the number of information bits storable in two cells is equalto log₂ 19. Therefore, the number of cells/bit becomes λ=(2n)/(k log₂p)=0.565.

In a word, according to the example of assignments of information valuesin FIG. 5, even if the reliability of data is maintained by ECC whileusing the pair cell, the cell occupation area can be shrunk by 0.565times.

The following description is given to multi-value writing to a cell in avariable resistance memory.

There are several types of variable resistance memory cells. They arethough roughly divided into the type that causes a variation inresistance value in accordance with formation of a filament by metalions and the type that causes a variation in resistance value inaccordance with contacts between molecules such as CNTs. The latter typeof those can be considered as an aggregation of micro-switches in asense. Therefore, the latter type is such that the cell resistance valueis stable, the retention property is excellent, and cell multi-valuingis relatively easy. On the other hand, the former type (hereinafter alsoreferred to as the “filament type”) is such that the filament itself isunstable and therefore the retention property is poor, and cellmulti-valuing is relatively difficult.

Even a cell of the filament type, multi-valuing can be realized bythinking filament formation processes. Then, filament formationprocesses for realizing multi-valuing a cell are described withreference to FIG. 6.

FIG. 6 is a diagram showing state variations of a cell in the memorysystem according to the embodiment. The cell in FIG. 6 is of thefilament type. It is a cell in an ion memory. FIG. 7 is a diagramshowing a relation between relative inter-ionic distances and activationenergy in the cell in the memory system according to the embodiment.

A filament can be formed in two stages. The first stage is a process ofcreating several clusters in an ion migrating medium while the secondstage is a process of coupling these clusters by the filament. Forrealizing these filament formation processes, the solid medium is set sothat a barrier potential Ec in the first stage becomes higher than abarrier potential Ef in the second stage. In the case of FIG. 7, thepotential for cluster formation is Ec≈1 eV and the potential forfilament formation between clusters is Ef≈0.8 eV. In a word, thedifference between the potentials for cluster formation and filamentformation is Eδ≈0.2 eV.

A variation in resistance value of the cell and a voltage V appliedacross the cell relate as follows. The medium in the reset cell containsisolated clusters remaining as shown with black circles in A of FIG. 6.Here, “reset” means turning the cell to a high resistance state. In thisstate, when the voltage V is applied between electrodes of the cell, Agions start to diffuse inside the medium as shown with white circles in Bof FIG. 6. Then, when the potential on the center of the Ag ion exceedsthe cluster formation potential Ec, clusters are formed betweenelectrodes of the cell. The average number of clusters, <n>, formed atthis time and the voltage V between electrodes establish a relationV=<n>Ec therebetween. Here, <n> is a value on the assumption thatclusters are formed at equal intervals between electrodes. When thevoltage V between electrodes is further maintained continuously, as thepotential between electrodes has already become equal to or higher thanthe filament formation potential Ef, formation of a filament starts asshown in C of FIG. 6. Then, formation of a conductive filament betweenelectrodes sets the cell. Here, “set” means turning the cell to a lowresistance state by formation of the conductive filament betweenelectrodes. The average number of clusters, <n>, is determined by aninitial voltage applied between electrodes, the number of applicationtimes and so forth. A multi-value level of the cell can be determined inaccordance with <n>.

For ensuring the retention property at the average number of clusters,<n>, the medium of the cell may be designed appropriately to set thepotential. This is because such the design prevents application of alarge voltage between electrodes of the cell and avoids an occurrence ofdisturbance. As a result, cluster sites remain after the filament almostdisappears. When a voltage is applied between electrodes so that avoltage exceeding the potential Ef is applied to each cluster siteagain, the cell is set and turned to a low resistance state. The voltageV applied between electrodes of the cell is considered almost inverselyproportional to <n>. Accordingly, the voltage V can be used todiscriminate multi-value levels while lowering the cell resistance.Namely, the voltage V at the time of setting again has a proportionalrelation with the cell current at that time. Therefore, the voltage Vcan be used to discriminate which one of the levels it has.

Raising the cell resistance requires activation energy exceeding thecluster formation potential Ec again so as to diffuse metal ions to theelectrode. Therefore, such a reverse bias voltage V is applied betweenelectrodes of the cell that allows every potential on <n> clusters toexceed Ec. Thus, metal ions passing beyond the potential barrier forcluster formation are collected to the electrode.

The cell having a resistance value variable in accordance with filamentformation operates on the basis of diffusion and collection of metalions. Therefore, it is required to invert the voltage V applied betweenelectrodes, resulting in bipolar operation.

In FIG. 6, a high resistance state is represented as ‘0’ data, and a lowresistance state is represented as ‘1’ data. In addition, datacorresponding to plural levels in a weak high resistance state, which isan intermediate state between the high resistance state and the lowresistance state, is represented as ‘L’.

Subsequently, as an example of the unipolar operable cell, a NT stackcell using CNT contact/noncontact is described. In the followingdescription of the memory system according to the embodiment, the caseof the use of a unipolar operating cell is exemplified. This pointshould be noted.

FIG. 8 is a diagram showing state variations of a cell in the memorysystem according to the embodiment. The cell shown in FIG. 8 is a NTstack cell using CNTs. FIG. 9 is a diagram showing a relation betweenrelative inter-CNT distances and activation energy in the cell in thememory system according to the embodiment.

A CNT has a nanoscale molecular structure excellent in electrical andphysical properties, and applications thereof to resistance variablememories have been studied in the past.

The characteristics of the NT stack cell are described here.

If the CNT is compared to a straw, the NT stack is like a bed containingstraws stacked disorderly. It has a structure of straws partly contactedand separated with/from each other. The contact between CNTs can bemaintained by the Van der Waals force. The structure of the NT stack canbe maintained by the stiffness of CNTs contacting by the Van der Waalsforce. When the NT stack is formed between electrodes to observe theelectric resistance of the NT stack, the resistance value varies inaccordance with the situation of contact between CNTs. NT stacks formedunder similar conditions exhibit almost similar resistance variations.As shown in A of FIG. 8, a NT stack cell in a high resistance state hasnot only contact parts between CNTs (black circles in A of FIG. 8) butalso many noncontact parts inside the NT stack. The contact/noncontactbetween CNTs can be maintained by the stiffness of CNTs and the Van derWaals force as described above. When a voltage is applied betweenelectrodes of a NT stack cell in a high resistance state, an attractiveelectrostatic force acts between noncontact CNTs. When this attractiveelectrostatic force overcomes the stiffness held by CNTs, a relativedistance between CNTs reduces. When the relative distance between CNTsreaches a certain distance, the Van der Waals force acts to make acontact between CNTs as shown in B of FIG. 8. A white circle in B ofFIG. 8 is a new contact part between CNTs. As a result, the resistancevalue of the NT stack lowers.

The number of contact parts between CNTs varies along with theapplication time of the voltage between electrodes. The state of contactbetween CNTs can be maintained even after removing the voltage betweenelectrodes. A difference in the number of contact parts between CNTscorresponds to the difference in level of the NT stack cell.

A return of the NT stack cell in a low resistance state to a highresistance state requires injection of phonons, that is, thermaloscillations into the NT stack. This makes it possible to oscillate CNTsintensively to separate contacted CNTs and return shapes of CNTs by thestiffness originally held by CNTs. For this purpose, a voltage forcausing Joule heat easily in the NT stack cell is applied betweenelectrodes of the NT stack to concentrate phonons on contact partsbetween CNTs.

In this connection, the potential of the Van der Waals force of the CNTis E₀≈5 eV as shown in FIG. 9. Therefore, overcoming the stiffness tobend CNTs and make a contact between non-contacted CNTs requires avoltage having a larger potential than 5 eV to be applied betweenelectrodes.

Hereinafter, the high resistance state of the NT stack cell may also berelated to ‘0’ data, and the low resistance state to ‘L’ data. In thecase of a multi-valued NT stack cell, one or more natural numbers arerelated to ‘L’.

The following description is given to a method of reversibly changingresistance states of a NT stack cell.

FIG. 10 is a graph showing relations among phonon energy within a NTstack, resistances of the NT stack, and potentials of the electric fieldwithin the NT stack in the memory system according to the embodiment.The lateral axis in FIG. 10 indicates average phonon energy e thatallows a CNT end to freely execute an oscillating motion. It isconsidered that the energy e is proportional to Joule heat caused byelectric energy added to the NT stack. When the voltage betweenelectrodes of the NT stack cell is defined as v, the current flowing inthe NT stack as i, and the resistance of the NT stack as r, then theenergy e is represented by v²/r or i²r. On the lateral axis, e=E₀indicates the phonon energy corresponding to the Van der Waals forcecaused between CNTs. At this point, the contacted CNTs separate fromeach other, thereby increasing the resistance r of the NT stack. Thisvariation is further affected by the situation of the electric field, orthe voltage potential, placed between CNTs. FIG. 10 shows an instance ofv<V₀ with the solid line and an instance of v>V₀ with the dashed linebecause the graph varies the situation greatly in accordance with thevoltage v. The voltage V₀ is an average voltage when the oscillatingmotion of a CNT end bends the CNT against the stiffness held by the CNTso as to make contact with another CNT. Namely, as shown by the arrow a1in FIG. 10, in the case of v<V₀, the phonon energy e rises even if theNT stack has any resistance r and, when e>E₀ is reached, the contactbetween CNTs can be eliminated. As a result, the NT stack resistancerises up to r=R₀. In addition, as shown by the arrow a2 in FIG. 10, evenif the NT stack has any resistance r in the case of v>V₀, it is bentuntil the CNT end makes contact with another adjacent CNT when e issmall. As a result, the NT stack resistance r falls down to the minimumvalue. Then, this NT stack resistance r is fixed by the Van der Waalsforce. When the phonon energy e is elevated, the oscillating motioneliminates the contact between CNTs. Then, when e>E₀ is reached, almostall contacts between CNTs can be eliminated. As a result, the NT stackresistance r becomes higher as shown by the arrow a3 in FIG. 10. As thebias of the electric field is large, however, the probability ofcontacts newly made between CNTs is also large. As a result, the NTstack resistance r has a value of around R_(f) larger than the minimumvalue. In a state of high phonon energy e, the magnitude relationbetween the voltage v and the voltage V₀ makes the NT stack resistance rcome and go between R_(f) and R₀ as shown by the arrows a4 and a5 inFIG. 10. On the other hand, in a state of low phonon energy e, the NTstack makes only a change to a low resistance in the case of v>V₀ and nochange to a high resistance as shown by the arrow a6 in FIG. 10.

In the state of high phonon energy e, even if e≦E₀ is reached in thecase of v<V₀, the NT stack maintains the same resistance R_(f) as thatin the case of e>E₀ as shown by the arrow a7 in FIG. 10.

In consideration of the above-described variations in the NT stackresistance r, a method of changing the NT stack resistance r isdescribed next.

Initially, a description is given to raising the NT stack resistance.

FIG. 11 is a graph showing a relation between phonon energy and voltagesacross electrodes of a NT stack cell when the NT stack resistance ismade higher in the memory system according to the embodiment. FIG. 11shows V²/r relative to the phonon energy e at every resistance.

In the case of v<V₀, the NT stack resistance becomes r=R₀ in a state ofhigh energy e. When the energy e lowers, the NT stack resistance ismaintained almost at r=R₀. This is utilized to raise the NT stackresistance.

With respect to the maximum resistance r=R₀ of the NT stack, the voltagev is made sufficiently smaller than the voltage V₀ so that v²/r becomesaround E₀ or below. In addition, with respect to the minimum resistancer of the NT stack, the voltage between electrodes of the NT stack cellis set to v=U₀ so that it becomes larger than E₀. In this case, untilthe NT stack resistance r becomes the minimum resistance, the phononenergy keeps e>E₀. Thereafter, the voltage v between electrodes of theNT stack cell is gradually made larger so as to prevent the cell currenti from increasing and make the voltage stay back from the voltage V₀.Further, even if the resistance r is high, the energy e can becontrolled to exceed E₀. In this case, the NT stack resistance r can bemade higher while the cell current i is maintained small. Thiscorresponds to the instance in which the higher the resistance r, thelarger the voltage v becomes in the case of constant energy e in FIG.11. In this case, the state varies as the arrow a1 in FIG. 11.

In this connection, in read operation, the voltage v applied betweenelectrodes of the NT stack cell is made equal to or lower than thevoltage U₀/3 to achieve 1/10 or below the energy required for making atransition to the high resistance state. This is required to prevent theNT stack resistance from rising. Therefore, in read operation, thecurrent sense is desirable because it can expect a larger cell currentflowing at the time of a lower resistance compared to the voltage sense.

Subsequently, a description is given to lowering the NT stackresistance.

FIG. 12 is a graph showing a relation between phonon energy and cellcurrent in the NT stack when the NT stack resistance is made lower inthe memory system according to the embodiment. FIG. 12 shows i²rrelative to phonon energy e at every resistance.

Lowering the NT stack resistance utilizes the fact that the NT stackresistance r lowers one-sidedly if the voltage applied betweenelectrodes of the NT stack cell satisfies v>V₀. In particular, itutilizes the fact that the NT stack resistance r becomes lowermost ifthe energy satisfies e≦E₀. When a voltage v=V₀ is applied betweenelectrodes of the NT stack cell having the maximum resistance r=R₀, acurrent i=I₀ flows. A constant voltage v>V₀ is applied across the NTstack by limiting the current to a current i≦J₀ (>I₀). At this time, inthe case of J₀ ²R₀<E₀, as the voltage v>V₀ is applied between electrodesof the NT stack cell, the NT stack resistance r lowers. In addition, asthe current is limited by i≦J₀, the voltage v sharply falls and the NTstack stabilizes at a low resistance. In addition, in the case of J₀²R₀>E₀, the NT stack resistance lowers to r=R_(f). At this time, if J₀²R_(f)<E₀ and J₀R_(f)>V₀, then the phonon energy e is small andaccordingly the resistance r lowers further. In other cases, the NTstack resistance stops at r=R_(f) and does not become lowermost. In anycase, the resistance lowers.

These variations in the resistance r correspond to the arrows a1 and a2in FIG. 12. If resistance lowering stays at the resistance r=R_(f),however, it is the case that the arrow a3 in FIG. 12 indicative of thevoltage v=V₀ would locate rightward from the dashed line indicative ofthe energy E₀, different from the case shown in FIG. 12. This casecorresponds to the case where it cannot be changed from the curveindicative of the resistance r=R_(f).

When the NT stack resistance is made lower, in practice, it is notrequired to always maintain a constant current. It is sufficient tosatisfy the conditions about the voltage v>V₀ and iV₀<E₀. Therefore, itis not required to thoughtlessly elevate the voltage v applied to thehigh-resistance NT stack for maintaining the constant current. If thelowered resistance increases the cell current i, the voltage v appliedacross the NT stack is lowered.

A method of accessing NT stack cells is described next.

The use of NT stack cells makes it possible to configure a cell array ofthe cross point type. In a word, the cell array of the cross point typeis structured to include plural bit lines BL, plural word lines WLintersecting these plural bit lines BL, and NT stack cells provided atintersections of plural bit lines BL and plural word lines WL.Hereinafter, a cell provided in the cell array of the cross point typemay also be referred to as a “CP cell” in particular. In addition, thecell array is divided in accordance with the size thereof into unit cellarrays each called a “MAT”.

In the case of the cell array of the cross point type, normally,accessing plural CP cells can be realized by selecting plural bit linesBL and one word line WL. Accordingly, the burden on the word line WLbecomes heavy. Therefore, the size of a MAT is determined inconsideration of the magnitude of an allowable burden on a word line WL,that is, the length of the word line WL. If plural short-fault CP cellslocate on the same word line WL in a cell array, disturbances caused bycurrent sneaking and so forth may prevent normal data write. Then, thefollowing description is given to a write sequence according to theembodiment for solving these problems. Hereinafter, the short-fault cellmay also be simply referred to as a “fault cell”.

The write sequence according to the embodiment includes an initial step,an all ‘0’ write step, and an ‘L’ write step. This write sequence mayalso be referred to as a “2-step write sequence” because writing data toan actual cell is achieved at two steps including the all ‘0’ write stepand the ‘L’ write step.

At the start, the initial step in the write sequence is described.

FIG. 13 is a diagram showing a bias state of a cell array at the initialstep in the write sequence in the memory system according to theembodiment. In FIG. 13, a cell MC shown by a black circle is a faultcell, an ‘L’-added cell MC is a cell MC in a low resistance state, andan ‘H’-added cell MC is a cell in a high resistance state. In addition,a selection line shown by a chain line is a non-access selection line,and a word line WL shown by a dashed line is a fault word line WL. Theseexpressions are similarly applied in FIGS. 14 and 15.

In the following description, a voltage for generating larger energythan phonon energy capable of eliminating the Van der Waals force in aNT stack cell is denoted with U₀, and a voltage slightly smaller thanthe voltage U₀ is denoted with U₀−d. In addition, a voltage for making acontact between NT stack cells against the stiffness of the NT stackcell is denoted with V₀, and a voltage slightly smaller than the voltageV₀ is denoted with V₀−d.

In the following description, word lines WL and bit lines BL may also becalled “selection lines”, the generic term thereof.

At the initial step, all bit lines BL are provided with the potentialU₀−d and all word lines WL with the potential U₀. A current is detectedin a selection line connected to a fault cell. The current is largerthan expected when a normal cell MC is reverse-biased. This can be usedto specify a fault selection line. The specified fault word line WL ishandled at the subsequent all ‘0’ write step as a word line WL providedwith the same fixed potential Vs as that on the access word line WL.

Subsequently, the all ‘0’ write step in the write sequence is described.

FIG. 14 is a diagram showing a bias state of a cell array at the all ‘0’write step in the write sequence in the memory system according to theembodiment.

At the all ‘0’ write step, the fault word line WL is provided with thepotential Vs while non-access bit lines BL are brought into the floatingstate and non-access word lines WL other than the fault word line WL arealso brought into the floating state.

On the other hand, all access bit lines BL targeted to simultaneousaccess are provided with the potential U₀. When a lower stationaryvoltage U₀ is applied to cells MC, phonons are injected into cells MC ina low resistance state as described before. Thus, the correspondingcells MC change to a high resistance state by the access word line WLand the fault word line WL. At this time, even if there are many cellsMC in a low resistance state, the voltage U₀ is lower, and the cellcurrent becomes smaller once the cells MC change to a high resistancestate. Therefore, the electrical load on the word line WL provided withthe potential Vs is light. To that extent, the number of access bitlines BL targeted to simultaneous access can be increased. In the cellsconnected to the fault word line WL except fault cells having faults inboth a NT stack and a diode and fault cells including a NT stack ofwhich resistance cannot be raised, resistances of cells MC are raised inorder at every access. Therefore, current passing through these cells MCare reduced in order. As a result, at the subsequent ‘1’ write step, ahigh voltage via the fault cell is not applied to non-access cells MCvia cells MC in a low resistance state. Accordingly, the influence ofdisturbance exerted on normal cells MC can be reduced greatly. Thiseffect becomes effective when a MAT is upsized.

At the all ‘0’ write step, the current flowing in the access word lineWL cannot be reduced. If all access cells MC cannot make a transition toa high resistance state, this access word line WL is regarded asconnected to a fault cell that includes a normal diode but has a faultonly in a NT stack. Then, this access word line WL is not accessed andthe all ‘0’ write step is interrupted. Thereafter, this access word lineWL is excluded from access targets at the subsequent steps.

Subsequently, the ‘L’ write step in the write sequence is described.

FIG. 15 is a diagram showing a bias state of a cell array at the ‘L’write step in the write sequence in the memory system according to theembodiment.

At the ‘L’ write step, an access cell MC targeted to ‘L’ write isprovided with the voltage V₀+d, and all other non-access cells MC arebrought into the floating state. In addition, only an access word lineWL is provided with the potential Vs and other selection lines arebrought into the floating state. As a result, the cell MC havingelectrodes provided with the voltage V₀ or above is only the access cellMC. Therefore, only the access cell MC changes to a low resistancestate. Multi-values can be discriminated by controlling the time ofapplying the voltage to the access cell MC.

In the initial stage of setting the potential V₀+d on bit lines BL, theaccess cell MC is in a high resistance state. Accordingly, no largecurrent flows therein and no load is imposed on the word line WL. Whenthe access cell MC starts to change to a low resistance state, currentstarts to flow in the access cell MC. In individual bit lines BL,current is limited because the later-described circuit executeshigh-impedance control. Therefore, the load on the word line WL isprevented from becoming extremely heavier.

The following description is given to potential variations on selectionlines at the time of the write sequence.

FIGS. 16 and 17 are diagrams showing potential variations on selectionlines at the time of the write sequence in the memory system accordingto the embodiment. FIG. 16 shows those on bit lines BL while FIG. 17shows those on word lines WL. In FIGS. 16 and 17, a chain line shows anon-access selection line, and a dashed line shows a fault word line WLand a non-access bit line BL connected to a fault cell. The time on thelateral axis indicates the initial step, the all ‘0’ write step and the‘L’ write step dividedly. These three steps are not required to becontinuous. A pause period may interpose between the steps, for example,at the time of accessing a cell MC. It is sufficient if the order ofsteps is kept. Namely, at the all ‘0’ write step, it is possible toconfigure a sequence as an independent process at every word line WL.

At the start, at the initial step, all bit lines BL are provided withthe potential U₀-d and all word lines WL with the potential U₀ in a MAT.At this step, a fault word line WL is specified.

Subsequently, at the all ‘0’ write step, both the access word line WLand the fault word line WL are provided with the potential Vs. Accessbit lines BL are provided with the potential U₀, which is then pulled uplittle by little from the potential U₀ as the resistance of the accesscell MC rises. FIG. 16 shows the situation of the potential on theaccess bit line BL, which is pulled up in two stages. The potential onthe access bit line BL may vary continuously or in stages more than two.Non-access bit lines BL are set in the floating state and accordinglyvary to the potential Vs* little by little. Non-access word lines WL arealso set in the floating state and accordingly reach the potential U₀*.

Subsequently, at the ‘L’ write step, among the access bit lines BL, theaccess bit line BL connected to the access cell MC targeted to ‘L’ writeis provided with the potential V₀+d. Thereafter, the impedance of thepower supply is raised so as to lower the potential on these access bitlines BL along with increases in cell current. Other access bit lines BLare set in the floating state and accordingly vary to the potential Vs*along with the lapse of time. The floating-state bit line BL connectedto the fault cell varies to the potential Vs** as the access bit line BLis provided with the potential V₀+d as described before. The access wordline WL maintains at the setting of the potential Vs. In contrast, allnon-access word lines WL including the fault word line WL arefloating-set and accordingly vary to the potential V₀*. They furthervary to the potential Vs* along with the reduction in potential on theaccess bit line BL.

Setting of multi-value levels includes simultaneously activatingindividual multi-bit sense amps at every certain time and executing acomparison at every sense amp with a reference value set at everymulti-value data to confirm the completion of write in the access cellMC individually. Then, connections with bit lines BL are closed in orderbeginning from the write-completed access cell MC.

Hereinafter, a memory system using 5-level/cell cells is described as anexample of the memory system according to the embodiment usingmulti-level/cell.

In MAT access, multi-bit simultaneous access is effective. Then, as theprecondition for multi-bit simultaneous access using reference cells,the following description is given to reference bit lines for generatingmulti-value reference values.

FIG. 18 is a schematic diagram of a configuration of reference bit linesin the memory system according to the embodiment. FIG. 19 is a circuitdiagram of a current source for reference bit lines in the memory systemaccording to the embodiment.

The memory system according to the embodiment uses a group of at least Mbit lines BL as reference bit lines RBL<m> (m=1 to M) at every MAT toset a high resistance state in cells MC on all reference bit lines RBL(hereinafter also referred to as “reference cells”). Hereinafter, agroup of M reference bit lines RBL may also be referred to as a“reference bit line group”. These M reference bit lines RBL areconnected via switch elements to one bus, that is, a reference localbus. Selection of the value of M and selection of the number ofreference bit lines RBL simultaneously connected to the reference localbus are determined by the situation of reference bit lines RBL and theinterval between resistances set at every multi-value. Selection of alarge M for simultaneous selection of many bit lines BL corresponds toextension of intervals between the corresponding resistancedistributions at multi-values.

A MAT of the cross point type is characterized in that reference bitlines RBL and access bit lines BL are always selected by a common wordline WL. Therefore, a reference bit line group is provided on severalparts of a long word line WL to arrange reference bit lines RBL andaccess bit lines BL in near environments desirably. In addition, a highresistance state is set in reference cells RC for the purpose ofreducing current flowing in the access word line WL as low as possibleand because a variable resistance memory cell is generally more stablein the high resistance state that in a low resistance state.

With reference to current in the reference local bus (standard current),a multi-value is written in an access cell. Comparison currents fordeciding multi-value levels are generated in a circuit shown in FIG. 19(hereinafter also referred to as a “comparison current generatorcircuit”).

The comparison current generator circuit is a current source forsupplying currents having 1:1, 1:¾, 1:½ and 1:¼ relations with thecurrent drawn into the reference local bus, which are defined ascomparison currents rf4, rf3, rf2 and rf1.

Individual circuit parts shown in FIGS. 18 and 19 are described below.

FIG. 18 shows only WL<1> and <2> as word lines for simple description.

The word line WL side of the reference bit line group is provided on aMAT end. An access word line WL is connected to the ground potential Vssvia a WL switch controlled by a control signal, from rdec. On the otherhand, on the bit line BL side of the reference bit line group, thereference bit lines RBL are connected to the reference local bus via aRBL switch controlled by a control signal, set/read.

The circuit serving as the current source for the reference local buscomprises a circuit indicated with A for supplying a power supply Vpp,and a circuit indicated with B for generating rf1-rf4 from the powersupply Vpp fed from the former circuit. The circuit indicated with Aincludes an NMOS transistor controlled by a control signal Vr andutilizes operation of this transistor in the saturation region to feedthe power supply Vpp to the circuit indicated with B. The circuitindicated with B includes a current mirror circuit composed of PMOStransistors controlled by the reference local bus. This current mirrorcircuit receives the power via a PMOS transistor controlled by a controlsignal, /accREAD, so that the current mirror circuit only operates asrequired.

The following description is given to the relation between the accessbit lines BL and the comparison currents generated at M reference bitlines RBL.

The condition of a voltage applied to a cell at the time of readoperation differs from that at the time of write operation. At the timeof read operation, as low a voltage as possible is applied so as tocause no variation in cell state. At the time of write operation, aconsiderably high voltage is applied so as to cause a variation in cellstate. Therefore, the comparison current is set to a value capable ofdiscriminating the multi-value level of a cell in read operation using alow voltage. The comparison currents rf1-rf4 for 5-level/cell describedabove are converted at access bit lines BL into voltages in accordancewith access operations.

FIG. 20 is a diagram illustrative of relations among comparison currentsat access operations in the memory system according to the embodiment. Aof FIG. 20 shows a comparison current at the time of write operation, Bof FIG. 20 shows a comparison current at the time of read operation, andC of FIG. 20 shows a comparison current for the reference cell.

The group of reference cells is applied with such a voltage that doesnot change the high resistance state of a cell. Therefore, thecomparison current to be generated becomes a reference level used at thetime of read operation. The values shown in C of FIG. 20 are referencevalues corresponding to reference levels. These reference values arereference values that allow current to flow out at first from Msimultaneously selected cells in high resistance states. This referencevalue is a value equal to M-times the value of current in the cell setin the high resistance state. The way for selecting M depends on thecell characteristics as described before. It should be noted that M isselected so as to cause no overlapped resistance distributions.

The values of reference levels are equal to M-times, M×¾-times,M×½-times and M×¼-times the average cell current of cells in highresistance states. Read operation decides the multi-value level of acell by comparing the cell current with these comparison currents. Inaccordance with a cell current Iread when a read voltage Vread isapplied, multi-value levels of a cell can be decided by 5 levels L0, L1,L2, L3 and L4 from the lower current value as shown in B of FIG. 20. Theresistance value of the cell is the highest at the time of L0 and thelowest at the time of L4.

So as to obtain the cell current Iread corresponding to these readcurrents, the resistance of the cell is set in write operation. At thetime of the all ‘0’ write, a voltage is applied to change a cell from ahigh resistance state to a low resistance state. This voltage is definedas a program voltage Vpro. Based on a cell current Ipro flowing at thetime of application of the program voltage Vpro, a comparison current isgenerated.

In the case of Vpro=α·Vread, the reference current at the time ofprogramming also becomes Ipro=α·Iread. Here, Iread is a comparisoncurrent at the time of read operation. Reference values are converted atindividual sense amps for bit lines BL and related to write of anymulti-value levels. The circuit used here is described later.

Hereinafter, a sense amp SA is described.

Next, the circuitry of the sense amp SA is described.

The embodiment uses a sense amp of the current comparison type so thatfine current comparison can be applied at the time of read operation orwrite operation to monitor the state of a cell at a high speed. In theembodiment, however, for the purpose of further elevating thesensitivity of the sense amp SA, the quantity of current flowing into acurrent mirror circuit on the cell current input side is made equal tothat on the reference current side so that the resistance value of thecell can be reflected more. The following description is given to thesense amp SA operative to compare the cell current flowing in a bit lineBL with the reference current flowing in a reference bit line RBL.

FIG. 21 is a circuit diagram of a sense amp in the memory systemaccording to the embodiment.

The sense amp SA includes PMOS transistors M0-M3, M8, M9, M12-M17 andNMOS transistors M4-M7, M10, M11 and M18. The transistors M0, M8, M10,M2 and M4 are serially connected between a certain supply potential Vddand the ground potential Vss. The transistor M6 has a source connectedto the gates of the transistors M0, M2 and M4, and a drain connected tothe ground potential Vss. The transistors M1, M9, M11, M3 and M5 areserially connected between the supply potential Vdd and the groundpotential Vss. The transistor M7 has a source connected to the gates ofthe transistors M1, M3 and M5, and a drain connected to the groundpotential Vss. The transistors M8 and M9 have gates, which receive acontrol signal, /act. The transistors M10 and M11 have gates, whichreceive a control signal, vLTC. The transistors M6 and M7 have gates,which receive a control signal, /se, for controlling the start ofsensing at the sense amp SA. An output node N2 between the transistorsM2 and M4 is connected to the gates of the transistors M1, M3 and M5 andthe source of the transistor M7. The output node N2 provides an outputsignal ‘out’. An output node N3 between the transistors M3 and M5 isconnected to the gates of the transistors M0, M2 and M4 and the sourceof the transistor M6. The output node N3 provides an output signal‘/out’.

The transistor M12 has a source connected to the drain of the transistorM16, a drain connected to an input node N0 between the transistors M10and M2, and a gate connected to the drain of the transistor M14. Thetransistor M16 has a source connected to a certain potential V1, and adrain connected to the sources of the transistors M12 and M14. The gateof the transistor M12 and the drain of the transistor M14 receive aninput signal ‘in’. The gate of the transistor M14 receives an inputsignal ‘/in’.

The transistor M13 has a source connected to the drain of the transistorM17, a drain connected to an input node N1 between the transistors M11and M3, and a gate connected to the drain of the transistor M15. Thetransistor M17 has a source connected to the potential V1, and a drainconnected to the sources of the transistors M13 and M15. The gate of thetransistor M13 and the drain and gate of the transistor M15 receive theinput signal ‘in’ The gates of the transistors M16 and M17 receive acontrol signal, /accREAD.

The transistor M18 has a source connected to the potential Vpp, and adrain connected to the potential V1. The gate of the transistor M18 isprovided with a potential Vw at the time of write operation and apotential Vr at the time of read operation.

This sense amp SA decides the resistance state of a cell by comparing acell current with a reference current. It is possible to execute fastreliable sensing even in a current comparison of several 10 nA or below.

The input stage of the sense amp SA includes a current mirror circuitcomposed of the transistors M12, M14 and M16, and a current mirrorcircuit composed of the transistors M13, M15 and M17. The input signal‘/in’ and the input signal ‘in’ contain currents configured equal. Thus,the sense amp SA allows the inflow of cell current while reflecting thevariation quantity relative to the reference cell current, and executesa current comparison at the time of the inflow of this cell current. Oneinput, in, is supplied with a flow of cell current and the other input,/in, with a flow of reference current.

The above two current mirror circuits operate on the potential V1. Thispotential V1 is generated by limiting the potential Vpp and the currentat the transistor M18. The transistor M18 is provided with the potentialVw at the time of write operation and the potential Vr at the time ofread operation. This makes it possible to switch between the potentialson bit lines BL at access operations.

Basic operation of the sense amp SA is described next.

FIG. 22 is a diagram of operating waveforms in the sense amp in thememory system according to the embodiment.

At the start, when the control signal, /act, is lowered from “H” to “L”in a state of a control signal, /se=“H” (step S0 in FIG. 22), a pair oftransistors M8 and M9 turns on. As a result, current flows in the senseamp SA.

Subsequently, the control signal, /accREAD, is lowered from “H” to “L”(step S1 in FIG. 22) to supply current into the access bit line BL andthe reference bit line RBL through the inputs of input signals ‘in’ and‘/in’. A difference between the cell current and the reference currentflowing at this time is amplified as the drain voltage difference andlatched by a pair of transistors M6 and M7, which are cut off afterpassing through the saturation region from the linear region.

Amplification of the current difference between the cell current and thereference current requires the control signal, /se, to be lowered from‘H’ to ‘L’ (step S2 in FIG. 22). As a result, the paired transistors M6and M7 both pass through the saturation region from the linear regionand turn off. At that time, a slight difference between the cell currentand the reference current causes a timing difference in transition tothe saturation region, which is converted into the drain voltage. If thesource potential on the transistor M6 is higher, the gate potentials onthe transistors M0 and M2 become higher and accordingly the transistorsM0 and M2 turn off. If the source potential on the transistor M7 ishigher, on the other hand, the gate potentials on the transistors M1 andM3 become higher and accordingly the transistors M1 and M3 turn off.Thus, the drain voltage difference in the pair of transistors M6 and M7is amplified.

A pair of transistors M10 and M11 is provided with a lowered gatepotential in the initial stage of sensing to suppress the conductance,thereby reducing the sense amp current supplied from the supplypotential Vdd. As a result, it reflects a cell current differencesupplied via a pair of transistors M12 and M13 more strongly inaccordance with the state of the sense amp SA.

In the initial stage of sensing, when the balance of the sense amp SAcollapses in accordance with the current difference between the cellcurrent and the reference current and then becomes stable, the controlsignal vLTC is raised from the potential Vrr to the potential Vpp higherthan the supply potential Vdd (step S3 in FIG. 22). As a result, thesense amp SA is supplied with the supply voltage to fully swing theoutput signal ‘out’ to the supply potential Vdd (S4 in FIG. 22). At thistime, the control signal /accREAD is raised to break the supply of thecell current and reference current to the sense amp SA.

The pairs of fine-patterned transistors contained in the sense amp SAhave variations caused by fluctuations in production steps. Therefore,the variations can be cancelled if current paths are configured byserially connecting as many elements as possible. Then, the sense amp SAuses three pairs of transistors including the pair of transistors M0 andM1, the pair of transistors M8 and M9 and the pair of transistors M10and M11 to configure the parts between the supply potential Vdd and theinput nodes N0 and N1. In particular, the pair of NMOS transistors M10and M11 suppresses the influence of variations in the pair of PMOStransistors M0 and M1 and the pair of PMOS transistors M8 and M9contained in a feedback loop in operation of the sense amp SA. Namely,the conductance of NMOS transistors M10 and M11 is suppressed to raisethe potentials on the drains and sources of PMOS transistors M0, M1, M8and M9 located closer to the supply potential Vdd than these transistorsM10 and M11, thereby raising the conductance of PMOS transistors M0, M1,M8 and M9. In a word, the conductance of PMOS transistors and NMOStransistors provides an action directing suppression of the influence ofvariations in respective characteristics. The gates of the pair of NMOStransistors M10 and M11 are supplied with the control signal vLTC.Accordingly, only when the control signal vLTC is amplified, this actionbecomes larger. Therefore, in the initial stage of sensing, the controlsignal vLTC is kept low. In the latter half of sensing in which data issettled, the data should be latched fast by elevating the control signalvLTC to raise the conductance of transistors. In the case of FIG. 22,the control signal vLTC is set to the potential Vrr different from thesupply potential Vdd until the time immediately before latching aftersensing and set to the higher potential Vpp at the time of latching.

The time difference between the fall of the control signal /accREAD(step S1 in FIG. 22) and the fall of the control signal /se (step S2 inFIG. 22) is adjusted so that the sense amp SA starts sensing after thecontrol signal /accREAD falls and the cell current and reference currentinjected into the sense amp SA are sufficiently reflected on the inputcurrent.

The sense amp SA creates a control signal, fin, indicating its ownactivation period to external. This control signal, fin, is a signalthat turns to ‘H’ in the case of /out=‘L’ and /se=‘L’. It is utilized,for example, to separate the bit line BL from the sense amp SA.

The reference input side of the sense amp SA for discriminatingmulti-value levels is detailed next.

FIG. 23 is a circuit diagram showing a circuit on the reference inputside of the sense amp in the memory system according to the embodiment.In the case of FIG. 23, the sense amp SA is ready for 5-level/cell.

The reference input side requires comparison currents corresponding tomulti-value levels (5 levels in the case of FIG. 23) as referencecurrents, which are appropriately switched for use at the time ofmonitoring the cell state. In addition, the voltage level at the time ofwrite operation differs from that at the time of read operation.Accordingly, it is required to switch between the states of thereference input in accordance with these levels.

All the comparison currents rf1-rf4 fed into the side /in are currentsflowing into the sense amp SA, which are generated at the reference bitlines RBL as described above. These comparison currents are not allowedto directly flow into the sense amp SA. The reason is as follows. Theway of viewing comparison currents in the case of the sense amp SA usedin write operation can be changed from that in the case of readoperation. This makes it possible to prevent a cell from making a failedtransition when a large voltage or current is given at the time of cellread operation. The comparison currents rf1-rf4 are selected by controlsignals L1-L4 and the selected current is fed to current mirrors.Current mirrors on the side /in are prepared two having differentmagnifications. A control signal /WRITE falls at the time of writeoperation and the reference current is magnified by a and fed into thesense amp SA for comparison with the cell current. A control signal/READ falls at the time of read operation and the reference current isfed at the same magnification into the sense amp SA. The meanings ofmagnifications at the time of write operation and at the time of readoperation are as described above.

When the cell current on the side, in, becomes larger than thecomparison current, that is, the cell resistance is made lower, theoutput signal becomes /out=‘L’.

An access system for selecting one word line WL and simultaneouslyselecting plural bit lines BL in one MAT is described next using asimple example.

FIG. 24 is a diagram showing a configuration of a current sensing systemin the memory system according to the embodiment. FIG. 24 shows two wordlines WL<1> and <2> and three bit lines RBL and BL<1> and <2>. Referencebit lines RBL are collectively represented by one.

A word line WL is selected when it is connected to the ground potentialVss via a WL switch controlled by the control signal, from rdec.

A bit line BL is selected by a BL switch. On/off control of the BLswitch requires switching in accordance with the sense state and soforth. Therefore, a signal input to the gate of a transistor containedin the BL switch is generated through logic operation. A method ofcontrolling the BL switch is as follows. Namely, a BL switch is alwayskept off by a control signal, /from cdec<m>, at ‘H’ when thecorresponding bit line BL is to be selected. Once the bit line BL isselected as the control signal, /from cdec<m>, turns to ‘L’, the BLswitch turns on/off in accordance with logic.

It is assumed here that the bit lines BL<1> and <2> belong to localbuses <1> and <2>, respectively. The local buses <1> and <2> areconnected to plural bit lines BL, and BL switches select BL<1> and <2>from those bit lines BL. The gates of transistors contained in the BLswitches receive the control signals, from cdec<1> and <2>, from acolumn decoder via inverters, respectively. The power supplies for theseinverters are connected to the inverse signals, /out<1> and <2>, ofoutput signals, out<1> and <2>, from the sense amps SA. A circuit of theinverter is shown in A of FIG. 24.

The bit lines BL are connected to the local buses via the BL switches,which are turned on when selected by a control signal, pr. The BLswitches are turned off on respective conditions in accordance withcontrol signals, fin<m>, from the sense amps SA.

The reference bit line RBL is connected to a reference local bus via atransistor contained in a RBL switch, which is controlled by a controlsignal, set/read, so as to turn on at the time of cell set operation andat the time of read operation. A comparison current generated at thereference bit line RBL is converted into a comparison current formulti-values at a reference current conversion unit and fed to severalsense amps SA commonly.

A sense amp SA is provided on each local bus. When the BL switch is cutoff by the output signal, out, from the sense amp SA, it can stopwriting to the bit line BL that has reached a certain current value.

The following description is given to a structure of a memory systemincluding a three-dimensionally structured cell array capable ofeffectively utilizing the memory system described above.

BL switches, WL switches, sense amps SA and so forth are provided on asemiconductor substrate beneath a MAT (cell array).

Selection lines in a MAT of the cross-point type are led out alternatelyfrom the opposite sides of the MAT to relieve the pitch of MATperipheral circuits. When transistors are formed in the vicinity of thesurface of the semiconductor substrate, however, an increase in thenumber of stacked MATs proportionally increases the formation area ofperipheral circuits. The reason is as follows. If the pitch of MATselection lines cannot be relieved and the peripheral circuits are laidout elongated in the extending direction of selection lines, theperipheral circuits are required by the number of stacked MATs to beaccessed individually.

Then, the following description is given to one of methods of solvingthe problem about the layout of the peripheral circuits.

FIG. 25 is a diagram showing a layout of arrangement regions of verticallines in a cell array seen from the stacking direction in the memorysystem according to the embodiment.

The layout described here utilizes no transistors formed on the surfaceof the semiconductor substrate but utilizes transistors formedthree-dimensionally instead. This transistor is a SGT (Surrounding GateTransistor) having a gate surrounding a conduction channel, or a TFT(Thin Film Transistor) having a conduction channel sandwiched betweengates. Poly-Si or an oxide semiconductor such as InGaZn-Oxide formed onthe surface of the semiconductor substrate is configured as theconduction channel. The transistors stand in pillar shapes around MATsin large numbers.

FIG. 26 is a diagram showing a cross-section of a transistor in thestacking direction in the memory system according to the embodiment.

The lowermost part of the structure shown in FIG. 26 is a layer ofconductor running parallel to the surface of the semiconductorsubstrate, which is turned to local word lines LWL/local bit lines LBL.A plug is raised on the local word line LWL/local bit line LBL, and agate-controlled, short pillar-shaped conduction channel is furtherformed thereon. Around the conduction channel, a conduction layer turnedto a gate is formed with an insulator layer sandwiched therebetween. Theconduction layer is formed by linking plural gates as a bus of gatelines around MATs along the sides of MATs as shown in FIG. 25. Pluralconduction layers are formed and plural conduction layers extend inparallel. On the pillar-shaped conduction channel, a plug is formed.This plug is connected to a pillar-shaped conduction layer serving as avertical line arranged around the upper MAT. This vertical line isconnected to a selection line in a specific MAT of plural stacked MATs.

FIG. 25 shows an example of SGT/TFT conduction channels arranged as evenas possible. Plural MATs are stacked from MAT<0> in the lowermost layerin order of MAT<1>, <2>, <3>. Selection lines in each MAT are connectedto vertical lines closer to the MAT in order from selection lines in thelower MAT so as not to collide with vertical lines. In the layout ofFIG. 25, four selection lines in each MAT are connected to one localword line/local bit line LWL/LBL selectively. The local word line/localbit line LWL/LBL corresponds to the local bus <m> shown in FIG. 24 andso forth. If it is assumed here that plural MATs are not selectedsimultaneously, the local word line/local bit line LWL/LBL is a commonline to all MATs. It is connected to an individual bit line BL or wordline WL in a MAT in accordance with a signal level supplied to gatelines around the MAT. The same local word line/local bit line LWL/LBL isconnected to four selection lines. As described above, selection linesare led out alternately from the opposite sides in each MAT.Accordingly, eight selection lines on a MAT are narrowed down to oneselection line by the layout shown in FIG. 25 and connected to the localword line/local bit line LWL/LBL immediately beneath the MAT. This makesit possible to relieve the pitch of local buses immediately beneath theMAT, thereby facilitating the layout of peripheral circuits such assense amps SA.

The above description has been given to the cell array that has astructure of stacked cell array layers (MATs) in which intersecting wordlines WL and bit lines WL are arranged in parallel with the principalplane of the semiconductor substrate. The following description is givento an example of a MAT (cell array) having a structure of bit lines BLextending vertically relative to the semiconductor substrate.Hereinafter, sometimes, a structure of memory cell layers stacked isreferred to as a “stacked structure”, a bit line extending in thevertical direction relative to the semiconductor substrate isrepresented by a “VBL”, and a structure of a cell array having bit linesVBL is called a “VBL structure”.

FIGS. 27-29 are diagrams showing layouts of the cell array in the memorysystem according to the embodiment. FIG. 27 shows a layout seen from thestacking direction, and FIGS. 28 and 29 are cross-sectional views in thevertical direction. In addition, a word line (second line) indicatedwith a thick frame in FIGS. 28 and 29 is a driven word line.

The VBL-structured MAT allows an arrangement of selection-line drivercircuits immediately beneath the MAT. Therefore, it is possible to solvethe increase in driver circuits around the MAT in accordance with thenumber of stacked cell array layers, which becomes a problem in astacked structure. Namely, an arrangement of bit lines VBL (first line)in the vertical direction (third direction) relative to thesemiconductor substrate can form driver circuits in a certain layoutindependent of the number of stacked cell array layers. In the case ofthe VBL structure, bit lines VBL are arranged vertically relative to thesemiconductor substrate. Therefore, the cell structure greatly differsfrom that in the case of a stacked structure including bit lines BLarranged in parallel with a semiconductor substrate.

In the case of the VBL structure, TFT layers are provided in two layerson the semiconductor substrate immediately beneath the stacked MATs, andconduction paths composed of AND-structured transistors are formed inthe vertical direction at bit lines VBL. In the VBL structure, bit linesVBL extending in the vertical direction are formed in pillar shapes and,as orthogonally intersecting therewith, word lines WL are stacked in thedirection (first direction) running parallel with the principal plane ofthe semiconductor substrate. For one bit line VBL, one word line WL isselected at each memory cell layer. Further, even-numbered word lines WLand odd-numbered word lines WL aligned in each memory cell layer arearranged so that they can be selected alternately from the oppositesides of the cell array layer. In each memory cell layer, word lines WLare not selected individually. Accordingly, the area of word-line drivercircuits can be reduced to that extent in comparison with the cell arrayhaving the stacked structure. Therefore, the area of selection-linedriver units can be reduced greatly in comparison with the cell arrayhaving the stacked structure. A cell MC is formed at an intersection ofa bit line VBL and a word line WL and driven by a voltage/currentapplied between the bit line VBL and the word line WL. A MAT includesplural TFT layers (transistor layers) stacked between the semiconductorsubstrate and the formation region of bit lines BL. In each TFT layer,plural TFTs are formed. A bit line VBL is selected by an AND circuit(logic circuit) composed of these TFTs. The selected bit line VBL isconnected to a global bit line GBL (third line) extending in thedirection (second direction) running parallel with the principal planeof the semiconductor substrate and orthogonally intersecting theextending direction of the word line WL. In the AND circuit composed ofTFTs, control signals BSL in two layers for selecting the bit line BLare arranged to form the gate of each TFT in the AND circuit. As shownin FIG. 28, if the same number of TFTs are formed in two TFT layers(transistor layers) immediately beneath the cell array layer, selectionof a pair from control signals BSL in two TFT layers makes it possibleto select a row of bit lines VBL aligned in the extending direction ofword lines WL. In addition, if TFTs are formed fewer in the first-layerTFT layer than those in the second-layer TFT layer, as shown in FIG. 29,the first-layer TFT layer makes it possible to configure the channelwidth by both surfaces of the TFT and form the gates on both sides.Thus, the first-layer TFT layer makes it possible to form TFTs havinglarger conductivity than those in the second-layer TFT layer, therebyobtaining larger conductance. A combination of selections of a logiccircuit and a word line WL makes it possible to select a row of cells MCalong the extending direction of the word line WL. These selected cellsMC are driven by a global bit line GBL. Selective driving of the globalbit line GBL makes it possible to control the number of cells MCsimultaneously selected and write operation/read operation. Also in thecase of the VBL structure, for control of the global bit line GBL, thesame system for multi-value write operation and read operation as thatin the case of the stacked structure can be applied to realizemulti-valuing of a memory system having a three-dimensional structure.

The TFT having a gate supplied with the control signal BSL is formed ofan oxide semiconductor. The TFT gate width cannot be made largerstructurally and accordingly cells are desirable if they are of thevoltage-driven type and resistance variable.

In a word, the VBL structure is more suitable for the voltage-driven ionmemory and so forth than NT cells and so forth requiring current forphonons as is said. In the case of the use of the ion memory, the centerof the pillar-shaped bit line VBL can be formed of a metal serving as anion source, for example, Ag.

In the case of the VBL structure, cell MC groups along bit lines VBL aredifferent in characteristic little by little from each other.Accordingly, variations arise in the conditions of setting multi-valuelevels at cells MC. Therefore, the above-described data storage on apair-cell basis becomes effective.

FIG. 30 is an equivalent circuit diagram of a VBL-structured cell arrayin the memory system according to the embodiment. In FIG. 30, TFTs areused as transistors.

As shown in FIG. 30, when the bit line VBL is driven by the controlsignal BSL and the word line WL shown with chain lines, the cell MC iselectrically connected to the global bit line GBL. In the stacked TFTs,the number of nodes is reduced every time passing through logic, andaccordingly the number of TFTs can be changed at every TFT layer. In thecase of FIG. 30, the number of TFTs in the lower-layer TFT layer closerto the global bit line GBL is designed to become lower so as to increasethe effective size of TFTs in the lower-layer TFT layer to gain lagerconductance. Depending on the convenience of the design, the number ofTFTs in the upper-layer TFT layer may be reduced.

The above description has been given to raising the information densityby cell multi-valuing and the configuration of the correspondingspecific memory system. In such the memory system, error correctionbecomes important in the presence of failed setting of a multi-valuelevel. Then, the following description is given to ECC processing usingan LMC capable of processing the error correction strongly and fast.

FIG. 31 is a functional block diagram of the memory system according tothe embodiment.

This memory system comprises a CPU, a memory controller, and a memorydevice composed of multi-value storable cells and so forth. In FIG. 31,the memory controller is a separate chip from the memory device thoughit may be mounted on the same chip as that for the memory device. TheCPU sends a command to the memory controller. The memory controllerreceives this command and sends the corresponding command to the memorydevice to control the memory device. The CPU, the memory controller andthe memory device are controlled by clocks. The clocks can be suppliedto the CPU, the memory controller and the memory device commonly thoughthey may be supplied via the CPU and the memory controller to thecontrol-targeted memory device.

M bits of binary data input to the memory controller via the data busare converted into the quantity in a finite field Zp, that is, a dataprocessing system in the memory controller. Batch-processed binary data,in the presence of a relation 2^(h-1)<p<2^(h) and in the presence of arelation 2^(g-1)<q<2^(g) with successive primes q and p (p<q), becomes aset of M bits that satisfies qg≦M<ph. This is a restriction determinedby LMC processing, and the relations among specific M, p and so forthare detailed later.

Binary data is processed at every M bits in the memory controller. Atthe start, binary data is converted into a p-adic expression in Zp at a‘binary to p-adic decode’ circuit block. Then, the values on digits ofthe p-adic expression are applied to create an LMC. At that time, binarydata is regarded as a 2^(h)-adic number divided by h bits and convertedinto a p-adic number.

ECC processing is executed in an ‘LMC ECC system’ circuit block.

Subsequently, coded elements in Zp are related to levels of amulti-valued cell composed of a pair cell in the memory device andsubjected to data conversion so that Lee metrics in Zp correspond todistances between cell levels. This conversion is executed in a ‘p-adic< > MLC binary mapping’ circuit block. In this ‘p-adic < > MLC binarymapping’ circuit block, elements in Zp are converted into pieces of datacorresponding to multi-values of a cell and stored in a page buffer.When the page buffer is filled with data, these pieces of data aretransferred from the memory controller to the memory device and writtenin pair cells. These operations are controlled by a command sent from a‘control’ circuit block to the memory device in accordance with thecommand input to the memory controller. The page buffer is configuredreflecting the relation between multi-value levels of a cell and pages.The elements in Zp are stored as multi-value levels of a cell after datais transferred from the page buffer to the memory device.

In reading data from the memory device, data corresponding to themulti-value level of the cell is read out in accordance with the commandreceived from the memory controller, and this data is transferred to apage buffer in the memory controller and held therein. The data held inthe page buffer is converted into a numeral in Zp at the ‘p-adic < > MLCbinary mapping’ circuit block. The converted data is subject to errorcorrection at the ‘LMC ECC system’ circuit block and restored to thecorrect LMC, and then converted into data expressed in a p-adic number.Thereafter, the data expressed in a p-adic number is converted into Mbits of binary data at the ‘p-adic to binary decode’ circuit block andprovided to external from the memory controller.

In the above ECC processing, simplification of computation processing atthe ‘LMC ECC system’ circuit block and the computation speed becomeimportant. Then, the following description is given to one of methodsfor making simpler the computation process of ECC processing.

At the start, an LMC is briefly described.

Symbols of a code C are representative elements in Z_(p), or integersc_(j) of 0 to p−1, as shown in Expression 1.

c _(j)εGF(p)=Zp,0≦c _(j) <p  [Expression 1]

The metrics of these integers are represented by Lee metrics |c_(j)|,and all Lee metrics |c_(j)| are represented by integers of p/2 or below.Lee metrics |c_(j)| are defined as in Expression 2.

0≦c _(j) <p/2:|c _(j) |=c _(j)

p/2<c<p:|c _(j) |=p−c _(j)  [Expression 2]

As the code C can be considered a row of n=p−1 symbols c_(j), it can berepresented by C=(c₁, c₂, . . . , c_(p-1)) A metric w(C) of the code Ccan be defined as the sum of Lee metrics |c_(j)| of the symbols as inExpression 3.

w(C)=|c ₁ |+|c ₂ |+

+|c _(p-1)|  [Expression 3]

The distance between codes can be defined by the sum of Lee metrics ofthe differences between the symbols corresponding to the codes. Here,two symbols c and y have a difference (Lee distance) d_(L) (c, y), whichis given in Expression 4.

d _(L)(c,y)=w(c−y)  [Expression 4]

In this case, the LMC is such a code that has the minimum distance of 2γbetween codes having a generator matrix G and a syndrome matrix H shownin Expression 5 and that can correct γ−1=E or lower Lee metric errors.

$\begin{matrix}{{G = \begin{bmatrix}1 & 2 & \ldots & ( {p - 1} ) \\1^{2} & 2^{2} & \ldots & ( {p - 1} )^{2} \\\; & \; & \ddots & \; \\1^{k} & 2^{k} & \ldots & ( {p - 1} )^{k}\end{bmatrix}}{H = \begin{bmatrix}1 & 2 & \ldots & ( {p - 1} ) \\1^{1} & 2^{1} & \ldots & ( {p - 1} )^{1} \\\; & \; & \ddots & \; \\1^{\gamma - 1} & 2^{\gamma - 1} & \ldots & ( {p - 1} )^{\gamma - 1}\end{bmatrix}}} & \lbrack {{Expression}\mspace{14mu} 5} \rbrack\end{matrix}$

When the word length of the code C is denoted with n and the word lengthof data is denoted with k, then γ=n−k where γ represents the redundantword length contained in the code C. If γ=n−k=3, then d_(L)(C)≧2γ=6,which makes it possible to obtain a code capable of correcting thevariation total sum of Lee metrics if it is equal to γ−1=ε=2 or below.

For the purpose of generating the LMC thus configured, input-converteddata is represented by a k-digit, p-adic number. Numerals on digits ofthis p-adic number correspond to the elements in Zp and therefore can beused as a data word X of LMC to obtain the code C through an operationC=XG using the generator matrix G. The obtained code is stored in thememory. Information about the error caused in the numeral in Zp storedis used as a code Y of LMC read out of the memory to obtain a syndromethrough an operation S=YH^(t) (H^(t) is a transpose of H) so that theposition and quantity of the error can be computed to correct the error.

The data word X is obtained as X=CG⁻¹ from the error-corrected codeexpression C where G⁻¹ is generally as in Expression 6.

                                [Expression  6]$G^{- 1} = {( {p - 1} )\begin{bmatrix}1^{- 1} & 1^{- 2} & \ldots & 1^{{- k} - 1} & 1^{- k} \\2^{- 1} & 2^{- 2} & \ldots & 2^{{- k} - 1} & 2^{- k} \\\vdots & \vdots & \ldots & \vdots & \vdots \\( {p - 2} )^{- 1} & ( {p - 2} )^{- 2} & \ldots & ( {p - 2} )^{{- k} - 1} & ( {p - 2} )^{- k} \\( {p - 1} )^{- 1} & ( {p - 1} )^{- 2} & \ldots & ( {p - 1} )^{{- k} - 1} & ( {p - 1} )^{{- k},}\end{bmatrix}}$

In the case of ε=2, G and H are as in Expression 7.

$\begin{matrix}{{G = \begin{bmatrix}1 & 2 & \ldots & ( {p - 2} ) & ( {p - 1} ) \\1^{2} & 2^{2} & \ldots & ( {p - 2} )^{2} & ( {p - 1} )^{2} \\\; & \; & \ddots & \; & \; \\1^{p - 4} & 2^{p - 4} & \ldots & ( {p - 2} )^{p - 4} & ( {p - 1} )^{p - 4}\end{bmatrix}}{H = \begin{bmatrix}1 & 1 & \ldots & 1 & 1 \\1^{1} & 2^{1} & \ldots & ( {p - 2} )^{1} & ( {p - 1} )^{1} \\1^{2} & 2^{2} & \ldots & ( {p - 2} )^{2} & ( {p - 1} )^{2}\end{bmatrix}}} & \lbrack {{Expression}\mspace{14mu} 7} \rbrack\end{matrix}$

From a data word A composed of k=p−4 elements in Zp, a syndrome createdby the code C=AG is created through S=YH^(t).

The following description is given to a relational expression requiredfor a specific circuit in the case of γ=ε+1=3, ε=2.

The binary data of the code C held in the memory device includes acollection of p−1 symbols. The code symbols themselves cause variationswhen suffer various disturbances. Then, the code C is restored from thecode Y in decoding. Prior to the decoding, a syndrome is sought at thestart. Each symbol is represented by h bits as binary-expressed data.

The syndrome can be sought as elements S₀, S₁, S₂ shown in Expression 8through an operation S=YH^(t) using a syndrome matrix H wherey_(j)=a_(j)+e_(j).

$\begin{matrix}{{{{\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}c_{j}}} = {{\sum\limits_{i = 1}^{k}\; {a_{i - 1}{\sum\limits_{j = 1}^{p - 1}\; (j)^{l + i}}}} = { 0\Rightarrow S_{1}  = {{\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}y_{j}}} = {\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}e_{j}}}}}}},\mspace{20mu} {S_{0} = {\Sigma \; e_{j}}}}\mspace{14mu}} & \lbrack {{Expression}\mspace{14mu} 8} \rbrack\end{matrix}$

The generator matrix G and the syndrome matrix H are configured tosatisfy GH^(t)=0 (mod p). Accordingly, a substitution of Y=C+E yieldsS=EH^(t). If E=(e₁, e₂, . . . , e_(p-1)), then a syndrome S₀ correspondsto the total sum of errors in code symbols as can be found. Only thesyndromes S provide information on errors and, on the basis of thesyndromes S, the correct code C is restored as follows.

Subsequently, the principle of decoding is described. Here, n=p−1 errorsymbols are classified into two sets J₊ and J⁻ as in Expression 9.

J ₊ ={jε(1,2,

,p−1);e _(j) <p/2}

J ⁻ ={jε(1,2,

,p−1);e _(j) <p/2}  [Expression 9]

Namely, they are classified into J₊ that is an arrangement of thepositions j of the code symbols c_(j) in the case of the symbol errorquantity e_(j)<p/2, and J⁻ that is an arrangement of the positions j ofthe code symbols c_(j) in the case of the symbol error quantitye_(j)>p/2. Polynomials λ(x), V(x) in the Galois field GF(p) areconfigured as in Expression 10 on the basis of these sets.

$\begin{matrix}{{{\Lambda (x)} = {\prod\limits_{j \in J_{+}}\; ( {1 - {jx}} )^{e_{j}}}}{{V(x)} = {\prod\limits_{j \in J_{-}}\; ( {1 - {jx}} )^{p - e_{j}}}}} & \lbrack {{Expression}\mspace{14mu} 10} \rbrack\end{matrix}$

Thus, the polynomial λ(x) is a polynomial that has a reciprocal numberof the position j of an error symbol in J₊ as a root and that has a Leemetric e_(j) of that code symbol as the multiplicity of the root. On theother hand, the polynomial V(x) is a polynomial that has a reciprocalnumber of the position j of an error code word symbol in J⁻ as a rootand that has a Lee metric, p−e_(j), of that code symbol as themultiplicity of the root. Decoding is a process of finally configuringthese polynomials only from the information on the syndrome S₁ andsolving them, thereby obtaining information on errors. In a word, it isrequired to seek a relation among these polynomials λ(x), V(x) and thesyndrome S₁.

Subsequently, as shown in Expression 11, when it is configured with aseries polynomial having each syndrome S₁ on a coefficient of thecorresponding degree, it is represented by a rational polynomial havingthe error quantity e_(j), the position j and the value of the symbol.

$\begin{matrix}{{S(x)} = {{\sum\limits_{l = 1}^{\infty}\; {S_{l}x^{1}}} = {{\sum\limits_{j = 1}^{p - 1}\; {e_{j}{\sum\limits_{l = 1}^{\infty}\; ({jx})^{1}}}} = {\sum\limits_{j = 1}^{p - 1}\; {e_{j}\frac{jx}{1 - {jx}}}}}}} & \lbrack {{Expression}\mspace{14mu} 11} \rbrack\end{matrix}$

From Expression 11, a relational equation shown in Expression 12 can beestablished among the polynomials λ(x), V(x) and the syndrome S(x).

$\begin{matrix}{{( \frac{\Lambda (x)}{V(x)} ){S(x)}} = {- {x( \frac{\Lambda (x)}{V(x)} )}^{\prime}}} & \lbrack {{Expression}\mspace{14mu} 12} \rbrack\end{matrix}$

Subsequently, the relational equation shown in Expression 12 is utilizedto seek the polynomials λ(x), V(x) from the syndrome S(x).

The syndrome S(x) is used to find a polynomial Ψ(x) at a degree of (γ−1)or lower shown in Expression 13.

$\begin{matrix}{{{{\Psi (x)}{S(x)}} \equiv {{- x}\; {\Psi^{\prime}(x)}\mspace{11mu} ( {{mod}\mspace{11mu} x^{3}} )}}{{{\Psi (x)} = {1 + {\sum\limits_{l = 1}\; {\psi_{1}x^{1}}}}},{\psi_{j} = {{- \frac{1}{j}}{\sum\limits_{i = 1}^{j}\; {\psi_{j - 1}S_{i}}}}}}} & \lbrack {{Expression}\mspace{14mu} 13} \rbrack\end{matrix}$

In an expansive expression of the polynomial Ψ(x), a coefficient ψ_(j)can be sought, from a comparison between the coefficients at thehomogeneous degree on both sides of the expression shown in Expression13, through an iterative method using the syndrome S_(i) and analready-determined coefficient ψ_(j-1). The coefficients ψ₀−ψ₂ of thepolynomial ψ(x) are sought from the syndrome S=(S₀, S₁, S₂). The resultsare shown in Expression 14.

ψ₀=1

ψ₁ =−S ₁

ψ₂=−(ψ₁ S ₁+ψ₀ S ₂)/2=(S ₁ ² −S ₂)/2  [Expression 14]

This polynomial Ψ(x) is a polynomial equivalent to λ(x)/V(x) while thepolynomials λ(x), V(x) are given key conditions shown in Expression 15.Therefore, they can be sought through a Euclid iterative method appliedto x³ and the polynomial Ψ(x) to remove constant multiples.

V(x)Ψ(x)≡λ(x)(mod x ³)

deg λ(x)+deg V(x)<3

λ(x) and V(x) are irreducible

deg λ(x)−deg V(x)≡S ₀(mod p)  [Expression 15]

Therefore, if the polynomial Ψ(x) can be configured from the syndromeS=(S₀, S₁, S₂), the syndrome S₀ can be used as the stop condition on theiterative method to seek the polynomials λ(x), V(x). Namely, theiterative method is applied to seek the polynomials λ(x), V(x) from aset of (S₀, Ψ(x)).

A Euclid iterative method applicable to x³ and Ψ(x) is described next.

The following description is given to a method for deriving polynomialsλ(x) and v(x) that satisfy a congruence equation, v(x)Ψ(x)≡λ(x) (modx³), using the Euclidean iterative method, in accordance with the stopcondition, deg λ(x)−deg v(x)≡S₀ (mod p). Of the polynomials λ(x) andv(x) derived, one that satisfies deg λ(x)+deg v(x)<3 is the errorsearching polynomial.

The Euclidean iterative method is a method for deriving functions f₀,f₁, . . . , f_(n) in turn using divisions of polynomials. Thesequantities have relations shown in Expression 16.

$\begin{matrix}{\mspace{79mu} {{{f_{0} = {{k_{0}f_{1}} + f_{2}}},\mspace{20mu} {f_{1} = {{k_{1}f_{2}} + f_{3}}},\ldots \mspace{14mu},\mspace{20mu} {f_{n} = {{k_{n}f_{n + 1}} + f_{n + 2}}}}\mspace{20mu} {{p_{- 1} = 0},\mspace{20mu} {p_{0} = 1},\mspace{20mu} {p_{n} = {{k_{n - 1}p_{n - 1}} + p_{n - 2}}}}\mspace{20mu} {{q_{0} = 0},\mspace{20mu} {q_{1} = 1},\mspace{20mu} {q_{n} = {{k_{n - 1}q_{n - 1}} + q_{n - 2}}}}\mspace{20mu} \begin{matrix}{{{p_{n}f_{n}} + {p_{n - 1}f_{n + 1}}} = {{( {{k_{n - 1}p_{n - 1}} + p_{n - 2}} )f_{n}} + {p_{n - 1}f_{n + 1}}}} \\{= {{p_{n - 1}( {{k_{n - 1}f_{n}} + f_{n + 1}} )} + {p_{n - 2}f_{n}}}} \\{= {{p_{n - 1}f_{n - 1}} + {p_{n - 2}f_{n}}}} \\{\vdots} \\{= {{p_{0}f_{0}} + {p_{- 1}f_{1}}}} \\{= f_{0}}\end{matrix}\mspace{20mu} \begin{matrix}{{{q_{n}f_{n}} + {q_{n - 1}f_{n + 1}}} = {{( {{k_{n - 1}q_{n - 1}} + q_{n - 2}} )f_{n}} + {q_{n - 1}f_{{n + 1}\;}}}} \\{= {{q_{n - 1}( {{k_{n - 1}f_{n}} + f_{n + 1}} )} + {q_{n - 2}f_{n}}}} \\{= {{q_{n - 1}f_{n - 1}} + {q_{n - 2}f_{n}}}} \\{\vdots} \\{= {{q_{1}f_{1}} + {q_{0}f_{2}}}} \\{= f_{1}}\end{matrix}\mspace{20mu} {{f_{0} = {{p_{n}f_{n}} + {p_{n - 1}f_{n + 1}}}},\mspace{20mu} {f_{1} = {{q_{n}f_{n}} + {q_{n - 1}f_{n + 1}}}}}{{{\begin{matrix}p_{n} & p_{n - 1} \\q_{n} & q_{n - 1}\end{matrix}} = {{\begin{matrix}{k_{n - 1}p_{n - 1}} & p_{n - 1} \\{k_{n - 1}q_{n - 1}} & q_{n - 1}\end{matrix}} = { {- {\begin{matrix}p_{n - 1} & p_{n - 2} \\q_{n - 1} & q_{n - 2}\end{matrix}}}arrow{{p_{n}q_{n - 1}} - {p_{n - 1}q_{n}}}  = {{( {- 1} )^{n - 1}( {{p_{1}q_{0}} - {p_{0}q_{1}}} )} = ( {- 1} )^{n}}}}},\mspace{20mu} {f_{n} = {{( {- 1} )^{n}( {{q_{n - 1}f_{0}} - {p_{n - 1}f_{1}}} )}\mspace{20mu}\therefore{f_{n} \equiv {( {- 1} )^{n + 1}p_{n - 1}{\Psi ( {{mod}\mspace{14mu} x^{3}} )}}}}},\mspace{20mu} {f_{0} = x^{3}},\mspace{20mu} {f_{1} = \Psi}}}} & \lbrack {{Expression}\mspace{14mu} 16} \rbrack\end{matrix}$

In this case, increases in n inevitably find f_(n) having a smallerdegree than the previous degrees at a certain n as shown in Expression16. This fact leads to the condition indicating the presence of thepossibility of deriving a solution that satisfies the stop condition inthe Euclidean iterative method.

In particular, with sequential introductions of p_(n) and q_(n) from thequotient polynomials k_(n) obtained in the process of divisions, thesepolynomials can satisfy simple relations. Therefore, f_(n) can berepresented by f₀, f₁, p_(n−1) and q_(n−1). Namely,f_(n)=(−1)^(n)(q_(n−1)f₀−p_(n−1)f₁) is established such that the degreesof p_(n−1) and q_(n−1) increase as the degree of f_(n) decreases.Because the degree of p_(n−1) increases as the degree of f_(n) decreasesin this way, the difference between degrees decreases inevitably tosatisfy the stop condition.

Generally, in the Euclidean iterative method, f_(n)=k_(n)f_(n+1)+f_(n+2)utilizes the sequential decreases in degree in relation to divisionswhile k_(n) assumes a first- or zero-degree equation here andaccordingly the degree cannot decrease always. Rather, the degree mayincrease but cannot exceed the degree of f₀. In any way, if the relationabout the factorization of the above polynomial Ψ(x) is established, therelation shown in Expression 16 can be established. Therefore, it ispossible to finally lower the degree to satisfy the stop condition onthe iteration.

When substitutions of f₀=x³, f₁=Ψ(x) are made to create a congruenceequation at x³, the stop condition on the iteration comes to degf_(n)−deg p_(n−1)=S₀ (mod 13). With respect to n that satisfies thisstop condition, if deg f_(n)+deg p_(n−1)<3, then substitutions ofλ(x)=f_(n), V(x)=p_(n−1) are possible.

On the other hand, if it is not possible to achieve such the degreerelation, it means the occurrence of an error that cannot satisfy theerror-correctable condition.

The use of the above-described Euclid iterative method makes Ψ(x) becomea second-order polynomial in the case of ε=2. As the polynomial of Ψ(x)has a smaller degree in this way, it is possible to compute operationresults of Ψ(x) for the coefficients of a specific easy generalpolynomial. The results are shown in Expression 17.

Case 1:

ψ₂≠0ψ₂≠ψ₁ ²

f ₀ =x ³

f ₁=ψ₂ x ²+ψ₁ x+1

f ₂={(ψ₁ ²−ψ₂)/ψ₂ ² }x+ψ ₁/ψ₂ ²

f ₃=ψ₂ ²/(ψ₁ ²−ψ₂)²

f ₄=0

p ⁻¹=0

p ₀=1

p ₁=(1/ψ₂)x−ψ ₁/ψ₂ ² x+1

p ₂={ψ₂ ²/(ψ₁ ²−ψ₂)}x ²/−{(ψ₁ψ₂/(ψ₁ ²−ψ₂)² }+x+ψ ₂ ²/(ψ₂−ψ₂)²

p ₃={(ψ₁ ²−ψ₂)²/ψ₂ ² }x ³

Case 2:

ψ₂≠0 ψ₂=ψ₁ ²

f ₀ =x

f ₁=ψ₂ x ²+ψ₁ x+1

f ₂=ψ₁/ψ₂ ²

f ₃=0

p ⁻¹=0

p ₀=1

p ₁=(1/ψ₂)x−ψ ₁/ψ₂ ²

p ₂={ψ₂ ²/ψ₁ }x ³

Case 3:

ψ₁≠0ψ₂=0

f ₀ =x ³

f ₁=ψ₁ x+1

f ₂=−1/ψ₁ ²

f ₃=0

p ⁻¹=0

p ₀=1

p ₁=(1/ψ₁)x ²−(1/ψ₁ ²)x+1/ψ₁ ³

p ₂=−ψ₁ ³ x ³

Case 4:

ψ₁=0ψ₂=0

f ₀ =x

f ₁=1

f ₂=0

p ⁻¹=0

p ₀=1

p ₁ =x ³  [Expression 17]

When substitutions of f₀=x³, f₁=Ψ(x)=1+ψ₁x+ψ₂x² are made to seekpolynomials using the Euclidean iterative method, four cases shown inExpression 17 arise in accordance with the conditions on coefficients ofΨ(x). The conditions in these cases depend on the presence/absence ofdivisions by zero. From the polynomials obtained at computationprocesses in the cases, a pair of f(x) and p(x) that satisfies the keycondition shown in Expression 15 is selected to seek λ(x) and v(x). Aspecific method for selecting a pair of f(x) and p(x) is describedlater.

The same method as the above-described one can be applied to seek afourth-degree and a third-degree polynomial in the case of ε=3 or apolynomial in the case of a higher ε as well. In this case, however, asthe case classification and so forth are complicated, the complexitybecomes equal to that in the case of the clock-operated circuit systemthat realizes the conventional Euclid iterative method as it is.Therefore, the above-described method is useful as fast directcomputations in the case of ε=2.

The above description has been given to the LMC, the ECC processing, andthe generation of the error searching polynomial using the Euclid methodin the case of ε=2 in relation to the embodiment. Then, the subsequentdescription is given to the conversion at the entrance of a p-adic Zpworld in ECC processing, encoding of data input to the memory system asZp data, decoding of the code read from the memory system, and theconversion at the exit of the p-adic Zp world. It is also given to aspecific example of the circuit for realizing these processing.

A “binary world” is an environment for processing an operation and soforth with binary-expressed data while a “p-adic Zp world” is anenvironment for processing an operation and so forth with data expressedby numerals in Zp.

FIG. 32 is a flow chart of data processing in the memory systemaccording to the embodiment.

A Zp-determining prime is denoted with p. The minimum number of bitsrequired for a binary expression of p is denoted with h. The number ofdigits in a 2^(h)-adic number expression of batch-processed data in thebinary world is denoted with k−1. The total quantity of Lee metrics ofcorrectable errors is denoted with ε=γ−1=2. In addition, n=p−1,k=n−γ=p−4 are given, and (k−1)h bits of data are subject to ECCprocessing in batch.

At the start, at the entrance of the p-adic Zp world in step S110, dataD_(k-1)=(d₀, d₁, . . . , d_(k-2)) expressed in a (k−1)-digit, 2^(h)-adicnumber is converted into data λ=(a₀, a₁, . . . a_(k-1)) expressed byk=p−4 elements in Zp. D_(k-1) is composed of k−1 pieces of h-bit data.The maximum number expressed by h bits is equal to max(h)=2^(h)−1. Whenthe number of multi-value levels of a cell is denoted with L, a relationcan be established as max(h−1)+1≦p<max(h)≦L.

Subsequently, at step S120, A=(a₀, a₁, . . . a_(k-1)) composed of k=p−4numerals a₀ to a_(p-5) in Zp is multiplied by a generator matrix G togenerate a code C composed of n=p−1 code symbols c₁ to c_(p-1). A codesymbol c_(j) is as shown in Expression 18.

$\begin{matrix}{C_{j} = {\sum\limits_{i = 0}^{p - 5}\; {(j)^{i + 1}a_{i}}}} & \lbrack {{Expression}\mspace{14mu} 18} \rbrack\end{matrix}$

Subsequently, at step S130, the code C is written in a cell array suchthat the code symbols c₁ to c_(p-1) are associated with multi-valuelevels of a cell.

Subsequently, at step S140, the code stored and held in the cell arrayis read out. The read data is a code Y derived from the code C possiblyhaving any error.

Subsequently, at step S150, the code Y is decoded. In decoding, anLMC-using ECC is applied to correct the error in the code Y to restorethe code C. Thereafter, based on A=CG⁻¹, data A is restored from thecode C. The process of error correction of the code Y is detailed later.

Finally, at the exit of the p-adic Zp world in step S160,binary-expressed data D_(k-1) is derived from the data A.

Next, decoding at step S150 shown in FIG. 32 is detailed.

In decoding, ECC processing for correction of errors in an LMC isexecuted mainly.

FIG. 33 is a flow chart of decoding in the memory system according tothe embodiment.

As described above, at step S140, the code Y is read from the cellarray. When the error contained in the code Y=(y₁, y₂, . . . , y_(p-1))is denoted with E=(e₁, e₂, . . . , e_(p-1)), the code Y can berepresented by Y=C+E.

In decoding, at the start, at step S141, from the code Y=(y₁, y₂, . . ., y_(p-1)) and S=YH^(t), a syndrome S=(S₀, S₁, S₂) is computed. Asyndrome component S₁ is as in Expression 19.

$\begin{matrix}{S_{1} = {{\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}y_{j}}} = {\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}e_{j}}}}} & \lbrack {{Expression}\mspace{14mu} 19} \rbrack\end{matrix}$

Here, as S₀=Σe_(j), in the case of S≠0 and |S₀|>2, errors have the totalquantity of Lee metrics equal to 3 or more and are uncorrectable.Therefore, this case is processed as no solution. The case of S=0 isprocessed as no error. In other cases, the flow goes to subsequent stepS142.

Subsequently, at step S142, for the upper limit, ε=2, of the number ofcorrectable code symbols, a solution searching polynomial Ψ(x)=(1, ψ₁,ψ₂) is derived from syndrome components S₀, S₁ and S₂ obtained at stepS141. Ψ(x) is as shown in Expression 20.

$\begin{matrix}{{{\Psi (x)} = {{1 + {\sum\limits_{j = 1}^{2}\; {\Psi_{j}x^{j}}}} = {1 + {\psi_{1}x} + {\psi_{2}x^{2}}}}}{\psi_{0} = {{1\psi_{1}} = {- S_{1}}}}{\psi_{2} = {{{- ( {{\psi_{1}S_{1}} + {\psi_{0}S_{2}}} )}/2} = {( {S_{1}^{2} - S_{2}} )/2}}}} & \lbrack {{Expression}\mspace{14mu} 20} \rbrack\end{matrix}$

Subsequently, at step S143, it is diverged based on ψ₁ and ψ₂ into threecases matching to the solution searching polynomial Ψ(x) obtainedthrough the Euclid method and the key conditions, and further divergedin each case based on S₀ to obtain a solution. Three cases are as shownin Expression 21.

Case 1:

ψ₂≠0 ψ₂≠ψ₁ ²

S ₀≡2:f ₁=ψ₂ x ²+ψ₁ x+1=0

S ₀≡0:f ₂={(ψ₁ ²−ψ₂)/ψ₂ ² }x+ψ ₁/ψ₂ ²=0,p ₁=(1/ψ₂)x−ψ ₁/ψ₂ ²=0

S₀≡2:

p ₂={ψ₂ ²/(ψ₁ ²−ψ₂)}x ²−{ψ₁ψ₂ ²/(ψ₁ ²−ψ₂)² }x+ψ ₂ ²/(ψ₁ ²−ψ₂)²=0

Case 2:

ψ₂≠0 ψ₂=ψ₁ ²

S ₀≡2:f ₁=ψ₂ x ²+ψ₁ x+1=0

S ₀≡−1:p ₁=(1/ψ₂)x−ψ ₁/ψ₂ ²=0

Case 3:

ψ₁≠0 ψ₂=0

S ₀≡1:f ₁=ψ₁ x+1=0

S ₀≡−2:p ₁=(1/ψ₁)x ²−(1/ψ₁ ²)x+1/ψ₁ ³=0  [Expression 21]

At step S143, if the condition of divergences is not applicable, or ifthe diverged solution searching polynomial Ψ(x) has no solution, it isnot possible to find any solution at ε=2. In this case, errors areuncorrectable, and accordingly decoding is stopped.

Subsequently, at step S144, a solution r obtained at step S143 is usedto restore the correct code C. When the position of a component y of theerror-containing code Y is denoted with t=r⁻¹, and the error quantity isdenoted with e_(t), the correct code C can be restored fromc_(t)=y_(t)−e_(t).

Finally, at step S145, the right inverse matrix G⁻¹ of the generatormatrix G is used to derive an element a_(j) in Zp from λ=CG⁻¹. Thus,data A=(a0, a1, . . . , a_(k-1)) is restored as k=p−4 symbols.

Next, ECC processing in the case of ε=2 is described. A system describedherein can be mounted on a chip by processing ECC asynchronously torealize fast processing and simplification.

FIG. 34 is a block diagram of ECC processing in the memory systemaccording to the embodiment.

Data input to the controller is binary data D having sets ofM=h(k−1)=h(p−5) bits. A M-bit, binary-expressed number is converted at aZp conversion block into data A having digits composed of elements inZp. The data A is converted at a ×G block into an LMC code C and writtenin a multi-valued memory device (cell array) from the memory controller.

The data read from the memory device is an LMC code Y, which containserrors caused by failed identification of multi-value levels. The code Yis restored at the following processing blocks to an errorless LMC andfurther restored to binary data D finally.

At the start, operation processing at an S=YH^(t) block is applied toderive a syndrome from the code Y. If the Lee metric of S₀ derived atthis operation processing is larger than 2, there are 3 or moreindividual error code components surely. In this case, error correctionmay not be achieved through the method of solving in the case of ε=2.Therefore, an NG signal is provided to external and an error-uncorrectedcode Y is sent directly to the output side.

In addition, if the syndrome vector is S=0, no error arises.Accordingly, the code Y is sent directly to the output side as expected.

In the case of other syndromes, the polynomials λ(x) and v(x), which canbe derived from the polynomial Ψ(x) and x³ through the Euclid iterationmethod, are directly derived by case classification of conditions oncoefficients of Ψ(x) regardless of the iteration method. Therefore, thepolynomial Ψ(x) is computed from the syndrome S=(S₀, S₁, S₂) to obtain asolution in accordance with the case classification of conditions.

The process of deriving a solution of the equation is diverged based onψ₁ and ψ₂ into three cases as shown in Expression 21, and furtherdiverged based on the value of S₀ at every case. If no solution is foundin each case, there are errors other than ε=2. This case is processed asno solution or NG, and an NG signal is provided. In this case, the codeY is sent directly to the output side as expected.

If solutions of the equation can be found, on the other hand, theposition of the error component and the error quantity are derived fromthese solutions. Namely, if it is possible to obtain a root r and themultiplicity n, the position t=r⁻¹ and the error e_(t) can be derived.Then, the derived error e_(t) is used in c_(t)=y_(t)−e_(t) to restorethe code C.

The restored code C is converted at a ×G⁻¹ block into elements in Zp ondigits of a p-adic number, and further converted at a binary conversionblock into binary data D, which is provided to external.

Next, a specific computation process is shown and described along theflow of ECC processing described with reference to FIG. 34.

The process of creating data to be written in a cell array includescomputations for creating a code C from symbols of data A. A specificexample thereof is shown in Expressions 22-25.

$\begin{matrix}{\mspace{79mu} {{m^{2k} \equiv {( {p - m} )^{2k}\mspace{11mu} {mod}\mspace{11mu} p}}\mspace{20mu} {m^{{2k} + 1} \equiv {{- ( {p - m} )^{{2k} + 1}}{mod}\mspace{11mu} p}}}} & \lbrack {{Expression}\mspace{14mu} 22} \rbrack \\{\mspace{79mu} {{C = {AG}}\mspace{20mu} {G = \begin{bmatrix}1 & 2 & \ldots & ( {p - 2} ) & ( {p - 1} ) \\1^{2} & 2^{2} & \ldots & ( {p - 2} )^{2} & ( {p - 1} )^{2} \\\; & \; & \ddots & \; & \; \\1^{p - 4} & 2^{p - 4} & \ldots & ( {p - 2} )^{p - 4} & ( {p - 1} )^{p - 4}\end{bmatrix}}}} & \lbrack {{Expression}\mspace{14mu} 23} \rbrack \\{\mspace{79mu} {{C_{j} = {{\sum\limits_{i = 0}^{p - 5}\; {(j)^{i + 1}a_{i}}} = {{\sum\limits_{i = 0}^{p - 5}\; {{{}_{}^{}(j)_{}^{i + 1}}a_{i}}} + {\sum\limits_{i = 1}^{p - 4}\; {{{}_{}^{}(j)_{}^{i + 1}}a_{i}}}}}}\mspace{20mu} {q_{j} = {\sum\limits_{i = 0}^{p - 5}\; {{{}_{}^{}(j)_{}^{i + 1}}a_{i}}}}{q_{p - j} = {{\sum\limits_{i = 0}^{p - 5}\; {{{}_{}^{}( {p - j} )_{}^{i + 1}}a_{i}}} = {{- {\sum\limits_{i = 0}^{p - 5}\; {{{}_{}^{}(j)_{}^{i + 1}}a_{i}}}} = {- q_{j}}}}}\mspace{20mu} {r_{j} = {\sum\limits_{i = 1}^{p - 6}\; {{{}_{}^{}(j)_{}^{i + 1}}a_{i}}}}\mspace{20mu} {r_{p - j} = {{\sum\limits_{i = 1}^{p - 6}\; {{{}_{}^{}( {p - j} )_{}^{i + 1}}a_{i}}} = {{\sum\limits_{i = 1}^{p - 6}\; {{{}_{}^{}(j)_{}^{i + 1}}a_{i}}} = r_{j}}}}}} & \lbrack {{Expression}\mspace{14mu} 24} \rbrack \\{\mspace{79mu} {{j < {p/2}}\mspace{20mu} {c_{j} = {q_{j} + r_{j}}}\mspace{20mu} {c_{p - j} = {{- q_{j}} + r_{j}}}}} & \lbrack {{Expression}\mspace{14mu} 25} \rbrack\end{matrix}$

As shown in Expression 22, an even-power of an element m in Zp iscongruent with an even-power of a Lee metric while an odd-power of theelement m in Zp is equal to a minus element of an odd-power of the Leemetric. This relation is utilized in the above computations to reduce byhalf the computational complexity for the element.

The computation of code symbols derived from the relation C=AG shown inExpression 23 is decomposed into an even sum Σ_(e) and an odd sum Σ₀ asshown in Expression 24, which are denoted with q_(j) and r_(j),respectively. In this case, symbols of a calculation code up to j<p/2can be derived as c_(j)=q_(j)+r_(j), c_(p-j)=−q_(j)+r_(j) as shown inExpression 25. Therefore, a decoding table of powers of elements can beused to simplify computations.

Specific computation blocks are described next.

FIGS. 35 and 36 are circuit diagrams of computation blocks in the memorysystem according to the embodiment. FIGS. 35 and 36 show code symbolcomponent computation blocks for deriving components q_(j) and r_(j) ofa code symbol c_(j) to be stored in a cell. In the shown case, primesare p=11, 13, 17, and 19.

As shown in FIGS. 35 and 36, in the case of the code symbol componentcomputation blocks, the number of circuit blocks and the number ofstages thereof vary in accordance with the value of a prime p. Thereason is as follows. In the code symbol component computation blocks,the numbers of even components and odd components alternate inaccordance with the prime p as the product of elements in Zp is executedtwo by two.

For example, q_(j) at p=13 can be obtained using the inputs on the leftside of the code symbol component computation block shown in FIG. 35.FIGS. 35 and 36 show general cases while the inputs and the number ofstages of ‘h bit AD mod p’ circuit blocks can be determined specificallyin accordance with the prime p. All circuit blocks contained in the codesymbol component computation block are static circuits, which require noclock synchronization and of which outputs are decided when the inputsare decided.

As described above, the code symbol c_(j) can be derived from the sum ofq_(j) and r_(j) and the difference therebetween. Besides, thecomputation processing in the embodiment frequently uses computationsfor deriving differences. The following description is given to acircuit block for executing the sum and difference computations.

FIG. 37 is a diagram showing a block symbol of an ‘h bit AD mod p’circuit block in the memory system according to the embodiment.

The ‘h bit AD mod p’ circuit block is a circuit operative to add theelements A and B in Zp together.

The ‘h bit AD mod p’ circuit block executes operation processing usingnumerical formulae shown in Expression 26.

A+B+FP0·p*=A+B mod p

FP0=1(if p≦A+B)

FP0=0(if A+B<p)

p*=inv(p)+1  [Expression 26]

Namely, if the sum of binary expressions of the numerals A and B issmaller than the binary-expressed prime p, then FP0=0, and if larger,then FP0=1. From the sum of binary expressions of the numerals A and B,FP0·p is subtracted to yield an element in Zp.

FIG. 38 is a circuit diagram of a computation block operative to derivea difference in the memory system according to the embodiment.

Subtraction of A from B requires obtaining −A in Zp at the start. −A isan element that becomes congruent with zero when A is added thereto. Anoperation of obtaining −A and the operation in the Zp world differ fromeach other in the condition of subtracting p for seeking the complementof A as an h-bit number. Therefore, an ‘h bit AD(2^(h)) mod p’ circuitblock is required as a new circuit block.

This ‘h bit AD(2^(h)) mod p’ circuit block executes operation processingusing numerical formulae shown in Expression 27.

inv(A)+(p+1)+FP1·p*=A*+p+FP1*p=A mod p

FP1=1(if p≦A*+p mod 2^(h))

FP1=0(if A*+p<p mod 2^(h))

p*=inv(p)+1  [Expression 27]

Namely, if the sum in binary of a prime p and the complement of A inh-bit binary is smaller than p, as a numeral within a range of h bits,that is, a numeral modulo 2^(h), then FP=0, and if larger, then FP1=1.FP1·p is subtracted to obtain the complement −A of A as an element inZp.

Further, the operation processing in the embodiment frequently usespowers of elements in Zp. The powers of elements in Zp can be simplyobtained by using a table when p is smaller, for example, p=13.

FIGS. 39-42 are power correspondence tables of elements in Zp in thememory system according to the embodiment. FIG. 39 shows an instance ofp=11, FIG. 40 shows an instance of p=13, FIG. 41 shows an instance ofp=17, and FIG. 42 shows an instance of p=19.

If decoders are configured on the basis of the power correspondencetables of elements in Zp shown in FIGS. 39-42, it is possible to obtainthe powers of elements in Zp without using any computation circuit.According to the nature of elements in Zp, even-powers of an element inthe case of an element m are equal to those in the case of p-m whileodd-powers of an element in the case of an element m are different insign from those in the case of p-m. Therefore, there is room forsimplifying the configuration of the decoder though FIGS. 39-42 show allexcept those becoming obvious one. In addition, even-powers of p-m areunderlined.

The following description is given to a computation process forgenerating a syndrome S from a code Y read from a cell.

Expressions 28-32 show a specific example of computations for generatingthe syndrome S from data Y in the case of ε=2.

$\begin{matrix}{\mspace{79mu} {A = {YH}^{t}}} & \lbrack {{Expression}\mspace{14mu} 28} \rbrack \\{\mspace{76mu} {H = \begin{bmatrix}1 & 1 & \ldots & 1 & 1 \\1^{1} & 2^{1} & \ldots & ( {p - 2} )^{1} & ( {p - 1} )^{1} \\1^{2} & 2^{2} & \ldots & ( {p - 2} )^{2} & ( {p - 1} )^{2}\end{bmatrix}}} & \lbrack {{Expression}\mspace{14mu} 29} \rbrack \\{\mspace{76mu} {{S_{0} = {{\sum\limits_{j = 1}^{p - 1}\; y_{j}} = {\sum\limits_{j = 1}^{p - 1}\; e_{j}}}}\mspace{20mu} {S_{1} = {{\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}y_{j}}} = {\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}e_{j}}}}}{S_{1} = {{\sum\limits_{j = 1}^{p - 1}\; {(j)^{1}y_{j}}} = {{\sum\limits_{j = 1}^{{({p - 1})}/2}\; {(j)^{1}y_{j}}} + {\sum\limits_{j = {{{({p - 1})}/2} + 1}}^{p - 1}\; {(j)^{1}y_{j}}}}}}{{\sum\limits_{j = {{{({p - 1})}/2} + 1}}^{p - 1}\; {(j)^{1}y_{j}}} = {{\sum\limits_{j = 1}^{{({p - 1})}/2}\; {( {p - j} )^{1}y_{({p - j})}}} = {( {- 1} )^{1}{\sum\limits_{j = -}^{{({p - 1})}/2}\; {(j)^{1}y_{- j}}}}}}\mspace{20mu} {S_{1} = {\sum\limits_{j = 1}^{{({p - 1})}/2}\; {(j)^{1}( {y_{j} + {( {- 1} )^{1}y_{- j}}} )}}}}} & \lbrack {{Expression}\mspace{14mu} 30} \rbrack \\{\mspace{79mu} {{u_{1} = {\sum\limits_{j = 1}^{{({p - 1})}/2}\; {(j)^{1}y_{j}}}}\mspace{20mu} {v_{1} = {\sum\limits_{j = 1}^{{({p - 1})}/2}\; {(j)^{1}y_{- j}}}}}} & \lbrack {{Expression}\mspace{14mu} 31} \rbrack \\{\mspace{79mu} {{S_{0,2} = {u_{0,2} + v_{0,2}}}\mspace{20mu} {S_{1} = {u_{1} - v_{1}}}}} & \lbrack {{Expression}\mspace{14mu} 32} \rbrack\end{matrix}$

In the case of ε=2, a matrix H is of 3 rows and p−1 columns as shown inExpression 29. When the sum of elements in Zp is divided by (p−1)/2, asmentioned in the description with reference to FIGS. 39-42, even-powersof an element in the case of an element j are equal to those in the caseof p−j while odd-powers of an element in the case of an element j aredifferent in sign from those in the case of p−j. Therefore, the syndromecomponent S₁ can be divided into two parts as shown in Expression 30. Inaddition, when u₁ and v₁ are defined as shown in Expression 31, syndromecomponents S₀ and S₂ can be represented by the sum of u₁ and v₁, and thesyndrome component S₁ can be represented by the difference between u₁and v₁.

The following description is given to a specific example of computationblocks for u₁ and v₁ shown in Expression 31.

FIGS. 43 and 44 are circuit diagrams of computation blocks in the memorysystem according to the embodiment. In the shown case, primes are p=11,13, 17 and 19. FIG. 43 shows an instance of p=11 and 19, and FIG. 44shows an instance of p=13 and 17.

The product of elements in Zp is executed two by two. Therefore,depending on the cases of even and odd (p−1)/2, the number of ‘x Zp’circuit blocks for product operation is changed so that theconfiguration of the computation block varies.

For example, in the case of p=13, the inputs on the left side of FIG. 44are used to obtain u₁. In addition, the inputs shown on the right sideof FIG. 44 are used to obtain v₁. All l-powered inputs in Zp areidentical.

FIGS. 43 and 44 show general cases while the inputs and the number ofstages of ‘h bit AD mod p’ circuit blocks can be determined specificallyin accordance with the prime p. All circuit blocks contained in a u₁/v₁computation block are static circuits, which require no clocksynchronization and of which outputs are decided when the inputs aredecided.

Hereinafter, an error searching process using a syndrome is described.

First, a polynomial that matches the key condition obtained through theEuclid method is used. Substitution of λ(x)=0 and V(x)=0 is made and acommon constant factor is factored out from the above polynomial. Theremaining polynomial is shown in FIG. 45.

FIG. 45 is a table showing divergences and syndromes of a searchingequation of Zp in the memory system according to the embodiment.

When a solution that satisfies the polynomial shown in FIG. 45 isderived in the case of each divergence, the place of the occurrence ofan error and the magnitude of the error can be obtained. In accordancewith the conditions for ψ₁ and ψ₂, there are three cases including cases1-3 as shown in FIG. 45. Each case further diverges in accordance withthe value of S₀. A J₊ row in each S₀ row corresponds to λ(x). Whenerrors e are +1 or +2, they each are +1 in the case of a single root and+2 in the case of double roots. A J⁻ in each S₀ row corresponds to V(x).When errors e are −1 or −2, they each are −1 in the case of a singleroot and −2 in the case of double roots.

As the condition-diverged polynomial is a quadratic equation at themaximum, the following description is given to a general method ofsolving this quadratic equation in Zp.

When a general quadratic equation is represented by x²+Ax+B=0, andx=y−α, α=A/2, D=(α²−Aα+B)=α₂−B are given, y²=D is established. Thisequation can be solved if Zp has a quadratic residue D. When one ofsolutions of y²=D is y (<p/2), p−y is also a solution. Thus, a quadraticequation of x has roots obtained as r1=y−α and r2=−y−α. If D is not aquadratic residue, y²=D has no solution, and the corresponding error isnot equivalent to that in the case of e=2.

The number of possible values of D in Zp is equal to p. Even in the caseof p=19, it is sufficient to execute decoding for p/2 or lower elementsof the elements in Zp. Therefore, only nine decoders are required toobtain solutions.

The use of the solutions of y²=D obtained above makes it possible todecide the positional quantities of error components depending onwhether the divergence is J₊ or J⁻.

Namely, when a quadratic equation has solutions r₁, r₂ and a linearsolution has a solution s, the error symbol position and the errorquantity in the case of J₊ are as in Expression 33.

S ₀=2:

t ₁ =r ₁ ⁻¹ ,t ₂ =r ₂ ⁻¹ :e=1

t ₁ =t ₂ :e=2

S ₀=1:

t=s ⁻¹ :e=1  [Expression 33]

In addition, the error symbol position and the error quantity in thecase of J⁻ are as in Expression 34.

S ₀=2:

t ₁ =r ₁ ⁻¹ ,t ₂ =r ₂ ⁻¹ :e=−1

t ₁ =t ₂ :e=−2

S ₀=1:

t=s ⁻¹ :e=−1  [Expression 34]

The following description is given to the forms of condition-divergedequations and solutions thereof in specific examples, and the majorquantities required in computation processes thereof.

A syndrome before divergence and the basic quantity obtained therefromare as in Expression 35.

S ₀ , S ₁ =−ψ₁,

S ₂ → a=2ψ₂ =S ₁ ² −S ₂ ,b=2(ψ₁ ²−ψ₂)=S ₁ ² +S ₂  [Expression 35]

The condition-diverged equations are given divergence numbers (s-1) to(s-6) and shown in Expressions A36-41, respectively.

(s-1):

ψ₂ x ²+ψ₁ x+1=0→x ²−(2S ₁ /a)x+(2/a)=0 α=−S ₁ /a

A=α ²−(2/a)

r ₁ =A ^(1/2) −α,r ₂ =−A ^(1/2)−α  [Expression 36]

(s-2):

x ²+{ψ₁/(ψ₁ ²−ψ₂)}x+1/(ψ₁ ²−ψ₂)=0

→x ²+(2S ₁ /b)x+(2/b)=0β=S ₁ /b

B=β ²−(2/b)

r ₁ =B ^(1/2) −β,r ₂ =−B ^(1/2)−β  [Expression 36]

(s-3):

x ²−(1/ψ₁)x+1/ψ₁ ²=0→x ²+(1/S ₁)x+(1/S ₁ ²)=0γ=1/(2S ₁)

C=γ ²−(1/S ₁ ²)=−3γ²

r ₁ =C ^(1/2)−γ=γ{(p−3)^(1/2)−1}r ₂ =−C ^(1/2)−γ=γ{−(p−3)^(1/2)−1}

p=11: r ₁=γ{(8)^(1/2)−1},r ₂=γ{−(8)^(1/2)−1}(8)^(1/2) =no solution

p=13:r ₁=γ{(10)^(1/2)−1}=5γ,r ₂=γ{−(10)^(1/2)−1}=6γ(10)^(1/2)=6,7

p=17: r ₁=γ{(14)^(1/2)−1},r ₂=γ{−(14)^(1/2)−1}(14)^(1/2) =no solution

p=19:r ₁=γ{(16)^(1/2)−1}=5γ,r ₂=γ{−(16)^(1/2)−1}=6γ(16)^(1/2)=4,15

(s-4):

ψ₁ x+1=0→S ₁ x+1=0

s=1/S ₁=2γ  [Expression 39]

(s-5):

(ψ₁ ²−ψ₂)x+ψ ₁=0→(b/2)x−S ₁=0

s=2S ₁ /b=2β  [Expression 40]

(s-6):

x−ψ ₁/ψ₂=0→x+2S ₁ /a=0

s=−2S ₁/α=2α  [Expression 41]

In the case of (s-1), as shown in Expression 36, α=−S₁/a and A=α²−(2/a)are required, and two roots are determined.

In the case of (s-2), as shown in Expression 37, β=S₁/b and B=N₂−(2/b)are required, and two roots are determined.

In the case of (s-3), as shown in Expression 38, γ=1/(2S₁) is required.Roots are decided by p, and two roots are determined. In the case ofp=11, 17, however, no corresponding quadratic residue exists andaccordingly no solution exists.

In the cases of (s-4) to (s-6), a linear equation is applied.

In the case of (s-4), as shown in Expression 39, one root is determinedby ε=2γ.

In the case of (s-5), as shown in Expression 40, one root is determinedby ε=2β.

In the case of (s-6), as shown in Expression 41, one root is determinedby ε=2α.

The underlines in Expressions 35-41 indicate the important quantitiesrequired at the time of seeking the positions of errors.

The following description is given to a computation process forobtaining the quantities from the syndrome S₀, S₁, S₂ in turn, and acomputation process for obtaining the final error position and quantityfrom the polynomials diverged on the basis of the obtained quantities.

Computation procedures of elements are shown in Expression 42, andsolutions of the diverged searching equations are shown in Expression43.

S ₀ ,S ₁ ,S ₂

a=S ₁ ² −S ₂ ,b=S ₁ ² +S ₂

−α=S ₁ a ⁻¹ ,β=S ₁ b ⁻¹,2a ⁻¹,2b ⁻¹

A=α ²−2a ⁻¹ ,B=β ²−2b ⁻¹

Case 1,Case 2,Case 3  [Expression 42]

Case 1:

a≠0,b≠0

S ₀=2:

(s-1)

t ₁ =r ₁ ⁻¹=(A ^(1/2)−α)⁻¹ e _(t) ₁ =1

t ₂ =r ₂ ⁻¹=(−A ^(1/2)−α)⁻¹ e _(t) ₂ =1

S ₀=0:

(s-5)

t ₁ =s ⁻¹=(2β)⁻¹ e _(t) ₁ =1

(s-6)

t ₂ =s ⁻¹=(2α)⁻¹ e _(t) ₂ =−1

S ₀=−2:

(s-2)

t ₁ =r ₁ ⁻¹=(B ^(1/2)−α)⁻¹ e _(t) ₁ =−1

t ₂ =r ₂ ⁻¹=(B ^(1/2)−α)⁻¹ e _(t) ₂ =−1

Case 2:

a≠0,b=0

S ₀=2:

(s-1)

t ₁ =r ₁ ⁻¹=(A ^(1/2)−α)⁻¹ e _(t) ₁ =1

t ₂ =r ₂ ⁻¹=(−A ^(1/2)−α)⁻¹ e _(t) ₂ =1

S ₀=−1:

(s-6)

t=s ⁻¹=(2α)⁻¹ e _(t)=−1

Case 3:

S ₁≠0,a=0

S ₀=1:

(s-4)

t=s ⁻¹=(2γ)⁻¹ =S ₁ e _(t)=1

S ₀=−2:

(s-3)

p=13

t ₁=(5γ)⁻¹=8γ⁻¹=3S ₁ e _(t) ₁ =−1

t ₂=(6γ)⁻¹=11γ⁻¹=9S ₁ e _(t) ₂ =−1

p=19

t ₁=(3γ)⁻¹=13γ⁻¹=7S ₁ e _(t) ₁ =−1

t ₂=(14γ)⁻¹=15γ⁻¹=11S ₁ e _(t) ₂ =−1  [Expression 43]

As shown in Expression 42, at the start, a and b are computed.Subsequently, −α, β, 2a⁻¹, 2b⁻¹ are computed from a and b. Subsequently,A and B are computed from −α, β, 2a⁻¹, 2b⁻¹. In the computation processup to now, the inverse element of a zero element is used as a zeroelement for convenience to advance the computation.

Subsequently, based on the obtained a, b, they are diverged into cases1-3 shown in Expression 43, and further diverged into groups ofsolutions corresponding to S₀ among the divergences. Through the abovecomputation processes, the positions t₁, t₂, t of error symbols and thequantities of the errors can be obtained.

The following description is given to correspondence relations amongelements in Zp, and inverse elements and square roots thereof present inmethods of solving a searching equation of Zp.

FIGS. 46-49 are correspondence tables of elements in Zp, and inverseelements, squares and square roots thereof in the memory systemaccording to the embodiment. FIG. 46 shows an instance of p=11, FIG. 47shows an instance of p=13, FIG. 48 shows an instance of p=17, and FIG.49 shows an instance of p=19.

With respect to the squares of elements in Zp, as an element m equal toor below p/2 corresponds to an element p-m, only the correspondencetable of elements of 1 to p/2 is sufficient. In FIGS. 44-47, elementsabove p/2 are underlined. As for the inverse elements of elements in Zp,a zero element has no meaning though it is related to zero forconvenience of computation to prevent a failure of computation. At thetime of divergence, however, a computation result of division by suchzero is excluded so as not to exert an influence on the process ofsolution searching. As for square roots of elements in Zp, they onlyexist in elements that are quadratic residues in Zp. Accordingly, FIGS.46-49 show them with ‘-’ In the absence of square roots for elements inZp, it is not possible to execute a root computation of the equation.Accordingly, solution searching is finished at that time. Thiscorresponds to the case where an NG signal is provided to external fromthe memory controller.

The following description is given to computation blocks operative tocompute the major quantities present in computation processes forderiving solutions of searching equations.

FIG. 50 is a circuit diagram of a computation block in the memory systemaccording to the embodiment. The computation block shown in FIG. 50 isoperative to compute A and B from syndrome elements S₁ and S₂. A circuitblock shown with an ellipse in FIG. 50 is a decoder based on thecorrespondence table of an element shown in ( ) and a power thereof. Thecomputation block further includes inverters, circuit blocks for seekingthe sum, and circuit blocks for seeking the product.

All circuit blocks contained in the computation block are staticcircuits, and processing by the computation block proceeds inasynchronous with clocks. Based on the quantities herein obtained,computations for seeking solutions diverge.

The divergences include comparisons of quantities and switching ofcomputation paths, which can be assembled by logics of asynchronouscircuits. Hereinafter, individual circuit blocks after divergence aredescribed.

The following description is given to circuit blocks operative tocompute t₁, t₂ and t representative of the positions of error-causedsymbols in accordance with divergences.

FIGS. 51-54 are circuit diagrams of computation blocks in the memorysystem according to the embodiment. FIG. 51 shows an instance of (s-1)or (s-2) shown in Expression 43, FIG. 52 shows an instance of (s-3)shown in Expression 43, FIG. 53 shows an instance of (s-4) shown inExpression 43, and FIG. 54 shows an instance of (s-5) or (s-6) shown inExpression 43. Part of circuit blocks in FIG. 51 is given ‘/’. The valueahead of ‘/’ is a value used in the case of (s-1) while the value behind‘/’ is a value used in the case of (s-2). Similarly, part of circuitblocks in FIG. 54 is given ‘/’. The value ahead of ‘/’ is a value usedin the case of (s-5) while the value behind ‘/’ is a value used in thecase of (s-6).

These computation blocks can be used before and after divergence. In aword, before divergence, the results computed previously using thesecomputation blocks are selected in accordance with the divergenceconditions. On the other hand, after divergence, divergences of (s-1) to(s-6) are executed in advance and a computation block corresponding toeach divergence is used in computation to obtain a result. When thesecomputation blocks are used before divergence, no corresponding elementmay exist in the computation process. Accordingly, ready for such thecase, each computation block prepares an output circuit for providing anNG signal to the outside of the memory controller. In addition, as for αand β, sign-different quantities (complements in Zp) are required.Accordingly, circuits for obtaining these quantities are provided.

As the error quantities are determined in accordance with respectivedivergences, they can be obtained with no computation. In the case oft₁=t₂, however, double roots exist. Therefore, the error quantitiesbecome ±2 depending on divergences. This point should be noted.

The following description is given to a process of converting an LMCcode C into symbols of data A in Zp after error correction. Relationalequations used in this conversion process are shown in Expressions43-47. In Expressions 46 and 47, a suffix ‘rev(m)’ indicates an inverseelement of an element m in Zp.

                                   [Expression  43]     A = CG⁻¹                                  [Expression  44]$G^{- 1} = {( {p - 1} )\begin{bmatrix}1^{- 1} & 1^{- 2} & \ldots & 1^{{- p} + 3} & 1^{{- p} + 4} \\2^{- 1} & 2^{- 2} & \ldots & 2^{{- p} + 3} & 2^{{- p} + 4} \\\vdots & \vdots & \ldots & \vdots & \vdots \\( {p - 2} )^{- 1} & ( {p - 2} )^{- 2} & \ldots & ( {p - 2} )^{{- p} + 3} & ( {p - 2} )^{{- p} + 4} \\( {p - 1} )^{- 1} & ( {p - 1} )^{- 2} & \ldots & ( {p - 1} )^{{- p} + 3} & ( {p - 1} )^{{- p} + 4}\end{bmatrix}}$                                    [Expression  45]$\mspace{79mu} {a_{i} = {{( {p - 1} ){\sum\limits_{j = 1}^{p - 1}\; {(j)^{{- i} - 1}c_{j}}}} = {( {p - 1} ){\sum\limits_{j = 1}^{p - 1}\; {( j^{- 1} )^{i + 1}c_{j}}}}}}$                                   [Expression  46]$a_{i} = {{( {p - 1} ){\sum\limits_{m = 1}^{p - 1}\; {(m)^{i + 1}c_{{rev}{(m)}}}}} = {( {p - 1} )\{ {{\sum\limits_{m = 1}^{{({p - 1})}/2}\; {(m)^{i + 1}c_{{rev}{(m)}}}} + {\sum\limits_{m = {{{({p - 1})}/2} + 1}}^{p - 1}\; {(m)^{i + 1}c_{{rev}{(m)}}}}} \}}}$${\sum\limits_{m = 1}^{p - 1}\; {(m)^{i + 1}c_{{rev}{(m)}}}} = {{\sum\limits_{m = 1}^{{({p - 1})}/2}\; {( {p - m} )^{i + 1}c_{{rev}{({p - m})}}}} = {( {- 1} )^{i + 1}{\sum\limits_{m = 1}^{{({p - 1})}/2}\; {(m)^{i + 1}c_{{rev}{({- m})}}}}}}$$\mspace{20mu} {a_{i} = {( {p - 1} ){\sum\limits_{m = 1}^{{({p - 1})}/2}\; {(m)^{i + 1}{( {c_{{rev}{(m)}} + {( {- 1} )^{i + 1}c_{{rev}{({- m})}}}} )\mspace{599mu}\lbrack {{Expression}\mspace{14mu} 47} \rbrack}}}}}$$\mspace{79mu} {Q_{i} = {\sum\limits_{m = 1}^{{({p - 1})}/2}\; {(m)^{i + 1}c_{{rev}{(m)}}}}}$$\mspace{20mu} {R_{i} =  {\sum\limits_{m = 1}^{{({p - 1})}/2}\; {(m)^{i + 1}c_{{rev}{({- m})}}}}arrow \mspace{20mu} {i\text{:}\mspace{14mu} {odd}} }$  a_(i) = (p − 1)(Q_(i) + R_(i))   i:  even  a_(i) = (p − 1)(Q_(i) − R_(i))

A right inverse matrix G⁻¹ of the generator matrix G is as shown inExpression 44. In addition, a symbol a_(i) of data is the sum of certainpowers of all inverse elements of the elements in Zp as shown inExpression 45.

All inverse elements are equal to all elements, and an inverse elementof p-m is equal to an element that corresponds to an inverse element ofm but has a minus sign. Accordingly, through the rearrangement of thesum and the division by the sum of m=1 to (p−1)/2, each a_(i) becomesthe sum of Qi and Ri and the difference therebetween as shown inExpression 47. Qi and Ri are the sum of the products of powers of(p−1)/2 from code components and components 1 in Zp. As shown inExpression 47, a_(i) is the sum of Qi and Ri if i is odd while a_(i) isthe difference between Qi and Ri if i is even.

Computation circuits of Qi and Ri are described next.

FIGS. 55 and 56 are circuit diagrams of computation blocks in the memorysystem according to the embodiment.

FIGS. 55 and 56 both show computation blocks for deriving Qi and Ri.FIG. 55 shows instances of p=11 and 19, and FIG. 56 shows instances ofp=13 and 17.

As the product of elements in Zp is executed two by two, the number of‘X Zp’ circuit blocks for product operation varies depending on whether(p−1)/2 is even or odd, and the circuitry of the computation blockvaries correspondingly.

In FIGS. 55 and 56, two quantities are shown for certain inputs. Theorder of these two quantities corresponds to the order of two quantitiesshown in the output. For example, in the case of p=13, Qi can beobtained using the inputs on the left side in FIG. 55 while Ri can beobtained using the inputs on the right side in FIG. 56. All(i+1)-powered inputs in Zp are identical.

FIGS. 55 and 56 show general cases while specific inputs and the numberof stages of ‘h bit AD mod p’ circuit blocks can be determined inaccordance with the prime p. The computation blocks shown in FIGS. 55and 56 are static circuits, which require no clock synchronization andof which outputs are decided when the inputs are decided.

As from the above, the present embodiment makes it possible to constructa memory system of the three-dimensional cross-point type having ahigher cell share.

OTHERS

While the embodiments of the present invention have been described,these embodiments are presented by way of example and are not intendedto limit the scope of the invention. These novel embodiments can beimplemented in a variety of other forms, and various omissions,substitutions and changes can be made without departing from the spiritof the invention. These embodiments and variations thereof would fallwithin the scope and spirit of the invention and also fall within theinvention recited in claims and equivalents thereof.

What is claimed is:
 1. A memory system, comprising: a cell array ofplural cells having three or more settable physical quantity levels andoperative to store a code composed of symbols expressed by elements in afinite field Zp (p is a prime), wherein a set of two cells is defined asa pair cell and a combination of physical quantity levels of said twocells contained in said pair cell is defined as a pair cell level,wherein said pair cell uses a pair cell level of plural pair celllevels, which maximizes or minimizes a physical quantity level of onecell contained in said pair cell, to assign elements in said Zp to saidpair cell levels, thereby storing symbols of said code.
 2. The memorysystem according to claim 1, wherein said pair cell assigns said paircell levels to elements in said Zp so that a variation of one level inphysical quantity level of one cell contained in said pair cell causes avariation within one in element in said Zp.
 3. The memory systemaccording to claim 1, wherein said pair cell assigns part of elements insaid Zp to plural levels of said pair cell levels.
 4. The memory systemaccording to claim 1, wherein said pair cell assigns said pair celllevels to elements in said Zp where p=11 when physical quantity levelsof said cells contained in said pair cell are 4 levels.
 5. The memorysystem according to claim 1, wherein said pair cell assigns said paircell levels to elements in said Zp where p=13 when physical quantitylevels of said cells contained in said pair cell are 5 levels.
 6. Thememory system according to claim 1, wherein said pair cell assigns saidpair cell levels to elements in said Zp where p=17 or 19 when physicalquantity levels of said cells contained in said pair cell are 6 levels.7. The memory system according to claim 1, wherein said code stored insaid cell array is a Lee metric code composed of symbols expressed byelements in said Zp.
 8. The memory system according to claim 1, whereinsaid plural cells each include a variable resistance element having astructure of nanotubes stacked.
 9. A memory system, comprising: a cellarray of plural cells each including a variable resistance element andhaving three or more settable resistance levels containing a highresistance state; and a comparison current generator circuit operativeto generate plural comparison currents for use in comparison with a cellcurrent flowing in said cell at the time of setting and deciding aresistance level of said cell, wherein said comparison current generatorcircuit uses a current, which flows in plural cells set in said highresistance state when accessed simultaneously in parallel, as areference current, and converts said reference current to generate saidcomparison currents.
 10. The memory system according to claim 9, whereinsaid comparison current generator circuit multiples said referencecurrent by a constant having a different value at every resistance levelto generate said plural comparison currents.
 11. The memory systemaccording to claim 9, wherein said plural comparison currents for use insetting said resistance level and said plural comparison currents foruse in deciding said resistance level have a constant-multiplicationproportional relation.
 12. The memory system according to claim 9,further comprising a sense amp operative to decide the magnituderelation between said comparison current and a cell current flowing in acell when said comparison current is supplied to said cell at the timeof deciding a resistance level.